The circuit of claim 1, further comprising: at least one additional circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process one signal of the plurality of signals within the parallel signal. view more

A method for coupling a plurality of Fibre Channel Arbitrated Loop (FCAL) nets, comprising: providing a plurality of separate backplane data paths; coupling a plurality of port integrated circuits by said separate backplane data paths, each integrated circuit having integrated thereon a port circuit and a portion of a crossbar switch; and coupling FCAL net interface to at least one FCAL net, and the portion of the crossbar switch, wherein each of said plurality of port integrated circuits has a priority level for access to busy destination nodes. view more

A packet switch for coupling a plurality of node loop (NL) nodes and/or Fibre Channel Arbitrated Loop network (FCAL nets) together to all concurrent data exchanges between a plurality of pairs comprised of one NL node or FCAL net and one other NL node or FCAL net, comprising: a crossbar switch; a protocol bus; a plurality of port circuits each having an input and an output for connecting to an FCAL net coupled to one or more NL nodes and capable of implementing a Fibre Channel loop protocol, and each having a crossbar switch port coupled to said crossbar switch; circuitry in each said port circuit and coupled to said protocol bus for maintaining a scoreboard table containing at least status information and a routing table containing data mapping destination addresses of NL nodes to port IDs; and wherein said port circuits function to establish connections between themselves by using destination addresses in Open (OPN) primitives received from source nodes to search said routing table to determine the ID of a remote port coupled to the destination node having the destination address in the OPN and, using that port ID to search said scoreboard table to determine status of the remote port, and then exchanging messages with said remote port to cause it to arbitrate for and take control of its local FCAL net and establish a data path via a particular channel through said crossbar switch and use said channel to transmit primitives and data frames between said source node and said destination node. view more

A packet switching switch for coupling a plurality of node loop (NL) nodes and/or Fibre Channel Arbitrated Loop network (FCAL nets) together to all concurrent data exchanges between a plurality of pairs comprised of one NL node or FCAL net and one other NL node or FCAL net, comprising: a crossbar switch; a protocol bus; a plurality of port circuits each having an input and an output for connecting to an FCAL net coupled to one or more NL nodes and capable of implementing a Fibre Channel loop protocol, and each having a crossbar switch port coupled to said crossbar switch; circuitry in each said port circuit and coupled to said protocol bus for maintaining a routing table containing data mapping destination addresses of NL nodes to port IDs and for maintaining a scoreboard table containing at least status information of remote ports; and wherein said port circuits function to establish connections between themselves by latching any Open (OPN) and Ready (RRDY) primitives received from source nodes and using destination addresses in OPN primitives received from said source nodes to search said routing table to determine the ID of a remote port coupled to the destination node having the destination address in the OPN, and then establishing a data path through said crossbar switch to said remote port and wherein each said port when it receives an OPN and any following RRDYs from another port via said crossbar switch, functioning to latch said OPN and RRDY and arbitrate for and take control of its local FCAL net, and continuing to try to take control of its local FCAL net until control is achieved, and when control is achieved, sending said OPN and any latched RRDYs to the destination node, and thereafter using said data path through said crossbar switch to send primitives and data frames back and forth between said source and destination nodes until the transaction is completed without ever storing any data frames. view more

A communication device configured to receive multiple serial data signals, comprising: a master timing generator adapted to generate a master timing signal; multiple receive-lanes each configured to receive an associated one of the multiple serial data signals, each receive-lane including a phase interpolator adapted to produce a sampling signal having an interpolated phase, and a data path adapted to sample and quantize the associated serial data signal in accordance with the sampling signal; and an interpolator control module coupled to each receive-lane, the interpolator control module being adapted to cause the phase interpolator in each receive-lane to rotate the interpolated phase of the sampling signal in the receive-lane at a rate corresponding to a frequency offset between the sampling signal and the serial data signal associated with the receive-lane so as to reduce the frequency offset between the sampling signal and the serial data signal. view more

A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:</claim-text> first circuitry implemented using current-controlled complementary metal-oxide semiconductor C<HIL><SP>3</SP></HIL>MOS e signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to process a first signal having a first frequency; and second circuitry implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuitry being coupled to the first circuitry and configured to process a second signal having a second frequency that is different than the first frequency, wherein the first circuitry comprises an input circuit that is implemented using the C3MOS logic, and is configured to deserialize the first signal into a plurality of lower frequency signals. view more