A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface location to a depth less than said first depth; the outer rim of each of said first and second source regions being laterally spaced along said first semiconductor surface from the lateral outer periphery of its said base region to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively, and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said first surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means and overlying said first and second channel regions; a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region; and at least said first base region being a cellular polygonal region; said cellular polygonal region being surrounded by said common conduction region; said first source region having the shape of an annular ring disposed within said cellular polygonal first base region. view more

A three-terminal power metal oxide silicon field effect transistor device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said depth of said base regions; said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region; source electrode means connected to said source regions and comprising a first terminal; gate insulation layer means on said first surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means, overlying said first and second channel regions and comprising a second terminal; a drain conductive region remove from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region and comprising a third terminal; each of said at least first and second spaced base regions of said opposite conductivity type having respective profiles which include relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region; at least said first base region being a cellular polygonal region; said cellular polygonal region being surrounded by said common conduction region; said first source region having the shape of an annular ring disposed within said cellular polygonal first base region; said relatively shallow depth region of said first base region surrounding the outer periphery of said relatively deep portion of said first base region. view more

The device of claim 7 wherein said shallow base regions partially underlie their respective source regions.

A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth; the outer rim of each of said first and second source regions being laterally spaced along said first semiconductor surface from the lateral outer periphery of its said base region to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively, and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said first surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means and overlying said first and second channel regions; said wafer including a further region of opposite conductivity type adjoining said lightly doped major body portion; and an electrode coupled to said further region. view more

The device of claim 19 wherein each of said at least first and second spaced base regions of said opposite conductivity type have respective profiles which include relatively shallow depth regions extending from said common conduction region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common conduction region; said shallow base regions partially underlying their respective source regions. view more