<INS-S DATE="20031230" ID="INS-S-00001"/>12. An improved tunneling region for use with an integrated circuit comprising:</claim-text> <i>a first layer of polysilicon; </i> <i>a first electron tunneling layer of thermal oxide formed over said first unneling layer of annealed deposited silicon dioxide formed over said first tunneling layer having a thickness less than 2000 Angstroms thick, said silicon dioxide layer being formed by low pressure chemical vapor deposition; and a second layer of polysilicon formed over said layer of deposited silicon dioxide, such that when a bias voltage is applied between said first layer of polysilicon and said second layer of polysilicon, electron tunneling will occur from said first layer of polysilicon to said second layer of polysilicon through said first and second electron tunneling layers. view more

<INS-S DATE="20031230" ID="INS-S-00002"/>13. A semiconductor device including means for electron tunneling, comprising:</claim-text> <i>a first conductive layer; </i> <i>an annealed silicon dioxide tunneling layer having a thickness less than top of said conductive layer, said silicon dioxide layer being formed by low pressure chemical vapor deposition; and a second conductive layer formed on top of said silicon dioxide layer, said first conductive layer acting as a source of tunneling electrons under an appropriate voltage bias condition, said second conductive layer serving as the receptor of said tunneling electrons. view more