A dynamic logic circuit, comprising: a dynamic logic block; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; and a delay coupled to the precharge transistor for simultaneously activating the precharge and evaluation transistors. view more

The dynamic logic circuit of claim 1 wherein the precharge transistor includes a gate and a source-to-drain path, and the delay is coupled to the gate of the precharge transistor.

The dynamic logic circuit of claim 1 including an anti-float circuit coupled to the precharge transistor.

The dynamic logic circuit of claim 4 wherein the anti-float circuit includes a latch.

The dynamic logic circuit of claim 1 wherein the precharge and evaluation transistors each include a gate and a source-to-drain path, and the dynamic logic circuit includes a clock signal node coupled to the gates of the precharge and evaluation transistors for receiving a clock signal having precharge and evaluation phases for switching the precharge transistor between an active state during the precharge phase and an inactive state during a major portion of the evaluation phase and for switching the evaluation transistor between an inactive state during the precharge clock phase and an active state during the evaluation clock phase. view more

The dynamic logic circuit of claim 6 wherein the delay is coupled between the clock signal node and the gate of the precharge transistor.

The dynamic logic circuit of claim 1 wherein the precharge transistor is a P-channel transistor and the evaluation transistor is an N-channel transistor.

A method of precharging and evaluating a dynamic logic circuit, the method comprising the steps of: switching a precharge transistor, using a clock signal, between an active state during a precharge clock phase and an inactive state during a major portion of an evaluation clock phase; switching an evaluation transistor between an inactive state during the precharge clock phase and an active state during the evaluation clock phase; delaying the precharge clock phase to the precharge transistor so that the precharge transistor is activated during a minor portion of the evaluation clock phase. view more