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AVM Technologies LLC v. Intel Corporation DC
- 1:15-cv-00033
- D. Del.
- Filed: 01/12/2015
- Closed: 05/19/2017
- Latest Docket Entry: 01/31/2019
- Judge: Richard G. Andrews
- PACER
1
Plaintiff
1
Defendant
1
Accused
Product
1
Patent-in-Suit
859
Days in
Litigation
-
AVM Technologies LLC v. Intel Corporation DC
- 1:15-cv-00033
- D. Del.
- Filed: 01/12/2015
- Closed: 05/19/2017
- Latest Docket Entry: 01/31/2019
- Judge: Richard G. Andrews
- PACER
Cause of Action
Willful Patent Infringement
Market Sector
Semiconductors
Court
Assigned Judge
Outcome Summary
Patent Information
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Validity & Enforceability
Claim # | Claim Text | Outcome |
---|---|---|
1 |
A dynamic logic circuit, comprising: a dynamic logic block; a precharge transistor; an evaluation transistor between the dynamic logic block and the precharge transistor; and a delay coupled to the precharge transistor for simultaneously
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|
Valid (102)
Entry 774 Entry 727 Entry 731 |
2 |
The dynamic logic circuit of claim 1 wherein the precharge transistor includes a gate and a source-to-drain path, and the delay is coupled to the gate of the precharge transistor.
|
Valid (102)
Entry 774 Entry 727 Entry 731 |
4 |
The dynamic logic circuit of claim 1 including an anti-float circuit coupled to the precharge transistor.
|
Valid (103)
Entry 774 Entry 727 Entry 731 |
5 |
The dynamic logic circuit of claim 4 wherein the anti-float circuit includes a latch.
|
Valid (103)
Entry 774 Entry 727 Entry 731 |
6 |
The dynamic logic circuit of claim 1 wherein the precharge and evaluation transistors each include a gate and a source-to-drain path, and the dynamic logic circuit includes a clock signal node coupled to the gates of the precharge and evaluation
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|
Valid (102 and 103)
Entry 774 Entry 727 Entry 731 |
7 |
The dynamic logic circuit of claim 6 wherein the delay is coupled between the clock signal node and the gate of the precharge transistor.
|
Valid (102 and 103)
Entry 774 Entry 727 Entry 731 |
9 |
The dynamic logic circuit of claim 1 wherein the precharge transistor is a P-channel transistor and the evaluation transistor is an N-channel transistor.
|
Valid (102)
Entry 774 Entry 727 Entry 731 |
21 |
A method of precharging and evaluating a dynamic logic circuit, the method comprising the steps of: switching a precharge transistor, using a clock signal, between an active state during a precharge clock phase and an inactive state during a
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|
Valid (102 and 103)
Entry 774 Entry 727 Entry 731 |
-
Infringement
Intel Corporation
- 1 Detail