A multiplexer circuit according to claim 15 further comprising: a third stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal; one of the third stage signal input terminals coupled to the second stage output terminal; the other one of the third stage signal input terminals coupled to receive a fourth input variable; and the third stage control input terminal coupled to receive a third control signal; whereby the circuit forms a 4:1 multiplexer. view more

A multiplexer circuit according to claim 16 further comprising: a fourth stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal; one of the fourth stage signal input terminals coupled to the third stage output terminal; the other one of the fourth stage signal input terminals coupled to receive a fifth input variable; and the fourth stage control input terminal coupled to receive a fourth control signal; whereby the circuit forms a 5:1 multiplexer. view more