A method for transferring a plurality of data units to a bus master from a respective plurality of memory locations at sequential memory location addresses in an address space of a secondary memory, for use with a host processing unit and a cache memory which caches memory locations of said secondary memory for said host processing unit, said cache memory having a line size of l bytes, and each data unit having a size equal to the largest size that can be transferred to said bus master in parallel, comprising the steps of: sequentially transferring data units to said bus master from said secondary memory according to a PCI-bus burst transaction, beginning at a starting memory location address in said secondary memory address space and continuing beyond at least first and second l-byte boundaries of said secondary memory address space, each l-byte line of said transaction requiring at least 8 data unit transfers to said bus master; and during the transfer of the data units for each entire N'th l-byte line in said step of transferring, initiating one and only one snoop access of said cache memory, said snoop accesses each specifying the respective N+1'th l-byte line and being initiated early enough such that they can be sampled by said host processing unit prior to completion of the transfer to said bus master of the last data unit in the respective N'th l-byte line, wherein said step of transferring comprises the step of transferring to said bus master three sequential data units including the last data unit before said first l-byte boundary and the first data unit beyond said first l-byte line, all at a constant rate, and wherein said step of transferring further comprises the step of transferring to said bus master three sequential data units including the last data unit before said second l-byte boundary and the first data unit beyond said second l-byte line, all at a constant rate. view more

A method according to claim 73, wherein said step of sequentially transferring data units continues further beyond a third l-byte boundary of said secondary memory,</claim-text> and wherein said step of transferring further comprises the step of ferring three sequential data units including the last data unit before said third l-byte boundary and the first data unit beyond said third l-byte line, all at a constant rate. view more

Controller apparatus for a computer system which includes a secondary memory having an address space, a bus master, a host processing unit and a cache memory which caches memory locations of said secondary memory for said host processing unit, said cache memory having a line size of l bytes, and each data unit having a size equal to the largest size that can be transferred to said bus master in parallel, said controller apparatus comprising circuitry which in a mode of operation, in response to a PCI-bus burst read transaction initiated by said bus master, sequentially transfers data units to said bus master from said secondary memory according to said PCI-bus burst transaction, beginning at a starting memory location address in said secondary memory address space and continuing beyond at least first, second and third l-byte boundaries of said secondary memory address space, each full l-byte line of said transaction requiring at least 8 data unit transfers to said bus master, a plurality of sequential data units bracketing at least said first, second and third l-byte boundaries being transferred to said bus master at a constant rate, said constant rate being dependent upon the frequency of a PCI-bus clock provided to said bus master; and during the transfer of the data units for each entire N'th l-byte line according to said transaction, initiates one and only one snoop access of said cache memory, said snoop access specifying the respective N+1'th l-byte line and being initiated early enough such that it can be sampled by said host processing unit prior to completion of the transfer to said bus master of the last data unit in the respective N'th l-byte line, said snoop accesses being sampled by said host processing unit in accordance with a host clock signal having a frequency that is at least twice said PCI-bus clock frequency. view more