A device comprising: a first Cyclic Redundancy Check (CRC) circuit configured to perform a first CRC operation on input data, the first CRC operation being performed using a first polynomial, the first polynomial being hardwired into the first CRC circuit; a second CRC circuit configured to perform a second CRC operation on the input data, the second CRC operation being performed using a second polynomial, the second polynomial being hardwired into the second CRC circuit; and a demultiplexer for receiving an instruction indicating that a CRC operation is to be performed and indicating which of the first and second circuits is to perform the CRC operation thereby providing an indicated circuit, the demultiplexer enabling the indicated circuit to generate a CRC output result based on the input data. view more

The device of claim 12, wherein the first and second CRC circuits each comprise: exclusive-or gates configured as a parallel decomposition of a serial CRC calculation circuit.