A double-gate FinFET device, comprising: a bulk silicon substrate; a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate; a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate; a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer; a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide; a gate which is formed on said first and second oxide layer; a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the thickness of said gate oxide layer is between 0.5 nm and 10 nm, and the thickness of said first oxidation layer is between 0.5 nm and 200 nm. view more

The device as claimed in claim 1, wherein the width of said Fin active region lies in a range between 4 nm and 100 nm.

The device as claimed in claim 1, wherein the height of said Fin active region from the surface of said bulk silicon substrate lies in a range between 10 nm and 1000 nm.

The device as claimed in claim 3, wherein the height of said Fin active region from the surface of said second oxide layer is between 5 nm and 300 nm.

The device as claimed in claim 1, wherein the parasitic capacitance between said gate and bulk silicon substrate is reduced by selecting the thickness of said second oxidation layer to be between 20 nm and 800 nm.

The device as claimed in claim 1, wherein the contact resistance is reduced by selecting the size of a contact region which is in contact with said metal layer to be greater than the width of said Fin active region and/or the length of said gate.

The device as claimed in claim 1, wherein said doping junction depth for the source/drain formed in said Fin active region, when the upper surface of said second oxide layer is taken as a reference level (0 nm), is around 0 nm to 50 nm above the reference level. view more

The device as claimed in claim 1, wherein said doping junction depth for the source/drain formed in said Fin active region, when the upper surface of said second oxide layer is taken as a reference level (0 nm), is around 0 nm to −50 nm below the reference level. view more

A double-gate FinFET device, comprising: a bulk silicon substrate; a Fin active region which is a all-shape single crystalline sililcon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate; a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate; a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer; a first oxide layer which is formed on the upper surface or said Fin active region with a thickness greater or equal to that of the gate oxide; a gate which is formed on said first and second oxide layer; a source/drain region whcih is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and a contact region and a metal layer which are formed at said source/drain and gate contact region, wherein the resistance of said Fin active region is reduced by enlarging the width of said Fin active region within the oxidation layer as it approaches the bulk silicon substrate. view more

The device as claimed in claim 1, wherein the two top corners of said Fin active region are chamfered through an oxidation and etching, or (and) annealing process in a hydrogen atmosphere.

The device as claimed in claim 2, wherein the height of said Fin active region from the surface of said bulk silicon substrate lies in a range between 10 nm and 1000 nm.

The device as claimed in claim 16, wherein the height of said Fin active region from the surface of said second oxide layer is between 5 nm and 300 nm.