A microcomputer data processing apparatus, comprising: a Central Processing Unit (CPU), a path configuring means, path control circuits connecting said CPU to said path configuring means, a plurality of contacts comprised of a plurality of distinct sets, wherein said CPU further comprises a dedicated memory address circuit, a dedicated memory data circuit, a dedicated memory control circuit and a dedicated power circuit, wherein said path configuring means further comprises a dedicated memory address circuit, a dedicated memory data circuit and a dedicated memory control circuit, wherein each said dedicated memory address, data, and control circuit includes a plurality of dedicated memory address, data, and control lines respectively, wherein said memory control lines are comprised of a read/write line, timing lines and status lines, first switch means comprised of at least three distinct parts for connecting said dedicated memory address, data, and control circuits of said path configuring means to each of said first three sets of contacts, and second switch means for connecting said dedicated memory address, data, and control lines of said path configuring means to said dedicated memory address, data, and control lines of said CPU respectively. wherein said first and second switch means assume a non signal-conducting state when said CPU power circuit is not supplied with power, wherein said lines of said CPU and said contacts assume a non-signal conducting state when said first and second switch means are in said non-signal conducting state, means for causing said first and second switch means to remain in said non signal-conducting state upon application of power to said CPU power circuit and to assume a signal-conductive state upon receipt of an appropriate signal from said CPU, and to assume a non signal-conducting state upon receipt of an appropriate signal from said CPU. view more