A system comprising: a bus capable of operation at a variable clock frequency; a first master device coupled to the bus, the first master device configured to provide a request to change a clock frequency of a high-speed clock in response to a predefined change in performance of the first master device, wherein the predefined change in performance is due to loading of the first master device as measured within a predefined time interval; and a programmable clock controller having an embedded computer program therein, the computer program including instructions to: receive the request provided by the first master device; provide the clock frequency of the high-speed clock as an output to control a clock frequency of a second master device coupled to the bus in response to receiving the request provided by the first master device; and provide the clock frequency of the high-speed clock as an output to control the variable clock frequency of the bus in response to receiving the request provided by the first master device. view more

The system of claim 14, wherein the instructions to provide the clock frequency of the high-speed clock as an output to control the variable clock frequency of the bus include instructions to adjust the clock frequency of the bus.

A system comprising: a bus capable of operation at a variable clock frequency; a first master device coupled to the bus; an arbiter coupled to the bus and coupled to the first master device, the arbiter configured to control flow of data on the bus; and a clock controller coupled to the arbiter and coupled to the first master device, the clock controller configured to output a clock frequency of a high-speed clock to control the variable clock frequency of the bus and to control a clock frequency of a second master device coupled to the bus, the clock controller configured to receive a request to change the clock frequency of the high-speed clock from the first master device, the request sent from the first master device in response to a predefined change in performance of the first master device, wherein the clock controller is configured to adjust the variable clock frequency of the bus in response to receiving the request from the first master device, and wherein the predefined change in the performance is due to loading of the first master device as measured within a predefined time interval. view more

The system of claim 18, wherein the predefined change in the performance of the first master device comprises a variation in load of the first master device.