A system for accelerated error-correcting code (ECC) processing comprising: a processing core for executing computer instructions and accessing data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes; one or more non-volatile storage media for storing the computer instructions and the data; and an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media, wherein the processing core, the non-volatile storage media, the I/O controller, and the computer instructions are configured to implement an erasure coding system comprising: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core and comprising: a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and a first sequencer for ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. view more

A system adapted to use accelerated error-correcting code (ECC) processing to improve the storage and retrieval of digital data distributed across a plurality of drives, comprising:at least one processor comprising at least one single-instruction-multiple-data (SIMD) central processing unit (CPU) core that executes SIMD instructions and loads surviving original data and surviving check data from a main memory and stores lost original data to the main memory, the SIMD CPU core comprising at least 16 vector registers, each of the vector registers storing at least 16 bytes;at least one system drive comprising at least one non-volatile storage medium that stores the SIMD instructions;a plurality of data drives each comprising at least one non-volatile storage medium that stores at least one block of the original data, the at least one block comprising at least 512 bytes;more than two check drives each comprising at least one non-volatile storage medium that stores at least one block of the check data;at least one first input/output (I/O) controller that transmits at least one block of computed lost original data from the main memory to a receiver; andat least one second input/output (I/O) controller that reads at least one block of the check data from the check drives and stores the at least one block of the check data to the main memory,wherein the processor, the SIMD instructions, the non-volatile storage medium and the at least one second I/O controller implement the accelerated ECC processing, comprising:a surviving data matrix comprising at least one vector and comprising at least one row of at least one block of the surviving original data in the main memory, each row of the at least one row being stored on a different one of the data drives, and a lost data matrix comprising at least one block of the lost original data in the main memory;a surviving check matrix comprising at least one row of at least one block of the surviving check data in the main memory, each row of the at least one row being stored on a different one of the check drives;a solution matrix that holds factors in the main memory, the factors of the solution matrix being for decoding the surviving original data and the surviving check data into the lost original data; anda thread that executes on the SIMD CPU core and comprising:at least one parallel multiplier that multiplies the at least one vector of the surviving data matrix by a single factor in the solution matrix to compute parallel multiplier results comprising at least one vector;at least one parallel adder that adds the at least one vector of the parallel multiplier results and computes a running total; anda sequencer wherein the sequencer:orders load operations of the surviving original data into at least one of the vector registers and load operations of the surviving check data into at least one of the vector registers;computes the lost original data with the parallel multiplier and the parallel adder; andstores the computed lost original data from the vector registers to the lost data matrix. view more