An apparatus in a microprocessor for determining a core clock frequency of a core clock signal, the core clock signal being derived from a bus clock signal that is provided from without the microprocessor, the apparatus comprising: ratio determination logic, configured to provide a fixed/variable clock ratio signal; and buffer/control logic, coupled to said ratio determination logic, configured to direct the microprocessor to set a core-to-bus clock ratio based upon said fixed/variable clock ratio signal and a plurality of clock ratio signals, wherein, if said fixed/variable clock ratio signal indicates a fixed core-to-bus clock ratio, said buffer control logic directs the microprocessor to disregard said plurality of clock ratio signals. view more

A microprocessor having a core-to-bus clock ratio, the core-to-bus clock ratio determining a first frequency of a core clock signal within the microprocessor, the core clock signal being derived from a bus clock signal provided from an external source, the microprocessor comprising: ratio determination logic, configured to provide a fixed/variable clock ratio signal, said ratio determination logic comprising: a fuse, configured to provide an electrical signal path for said fixed/variable clock ratio signal; buffer/control logic, coupled to said ratio determination logic, configured to convert a state of said electrical signal path into a voltage level, said voltage level being in a default state if said fuse is intact and in an altered state otherwise; and a selective clock multiplier, coupled to said buffer/control logic, configured to receive the bus clock signal and said voltage level, for generating the core clock signal, wherein the first frequency of the core clock signal is a multiple of a second frequency of the bus clock signal, and wherein, when said voltage level is in said altered state, said selective clock multiplier is unresponsive to clock ratio signals, said clock ratio signals prescribing said multiple when said voltage level is in said default state. view more

An apparatus in a microprocessor for generating a core clock signal having a configurable frequency or a fixed frequency, the apparatus comprising: a selective clock multiplier, for receiving a system bus clock signal, and for generating the core clock signal from said system bus clock signal, wherein a first frequency of the core clock signal is a multiple of a second frequency of said system bus clock signal; buffer/control logic, coupled to said selective clock multiplier, for enabling/disabling a plurality of clock ratio signals to prescribe said multiple during normal operation of the microprocessor; and a fuse, coupled to said buffer/control logic, capable of being blown during fabrication of the microprocessor, wherein blowing said fuse causes said buffer/control logic to disable said plurality of clock ratio signals and to fix said multiple to a predetermined value. view more