Semiconductor testing fixture and fabrication method thereof
First Claim
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1. A semiconductor testing fixture, comprising:
- a substrate having a plurality of testing regions;
a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions; and
a dielectric layer filling a space between two of the plurality of testing probes,wherein each of the plurality of testing probes comprises;
a first testing tip;
an insulation layer formed on a side surface of the first testing tip; and
a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer, and an end surface of the insulation layer levels with an end surface of the first testing tip and an end surface of the second testing tip.
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Abstract
A semiconductor testing fixture is provided. The semiconductor testing fixture includes a substrate having a plurality of testing regions; and a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions. Etch of the testing probes comprises a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.
11 Citations
18 Claims
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1. A semiconductor testing fixture, comprising:
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a substrate having a plurality of testing regions; a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions; and a dielectric layer filling a space between two of the plurality of testing probes, wherein each of the plurality of testing probes comprises; a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer, and an end surface of the insulation layer levels with an end surface of the first testing tip and an end surface of the second testing tip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for fabricating a semiconductor testing fixture, comprising:
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providing a substrate having a plurality of testing regions; and forming a plurality of testing probes with a predetermined distribution pattern on the substrate in each of the plurality of testing regions, comprising; forming a first metal layer on a surface of the substrate; forming a plurality of first testing tips with the predetermined distribution pattern on the substrate in each of the plurality of testing regions by etching the first metal layer; forming an insulation material layer covering top and side surfaces the plurality of first test tips on the surface of the substrate; performing a mask-less etching process on the insulation layer to form an insulation layer on side surfaces of the first testing tips; forming a second metal layer covering side surfaces of the insulation layer and the top surfaces of the first testing tips on the surface of the substrate; and performing a mask-less etching process to form the second testing tips on the side surfaces of the insulation layer, wherein each of the plurality of testing probes comprises; a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification