System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage

• US 10,001,953 B2
• Filed: 12/15/2016
• Issued: 06/19/2018
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Puthiyedath, Leena K., Fanning, Blaise, Opferman, Toby, Crossland, James B.
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US15/380,266
• Publication Number:
  US 20170139649A1
• Time in Patent Office: 551 Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1004 Compatibility, e.g. with legacy hardware
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

Claims

1. A computing system, comprising:

a processor to execute software;

memory coupled to the processor, the memory comprising non-volatile random access memory, the non-volatile random access memory partitioned into a first partition that is byte addressable by the processor, the non-volatile random access memory partitioned into a second partition that is block addressable by the processor; and

,

a memory controller coupled to the non-volatile random access memory to perform a memory access operation to access the non-volatile random access memory in response to a request from the software for access to the second partition, wherein, the software comprises a kernel level driver to translate a block address for a memory access operation into the second partition into a non-volatile random access memory address.

2. The computing system of claim 1 wherein the first partition is accessed at cache line granularity.

3. The computing system of claim 1 wherein the non-volatile random access memory is coupled to the memory controller through a dual data rate memory bus.

4. The computing system of claim 1 wherein the kernel level driver and the second partition are to implement a file system.

5. The computing system of claim 4 wherein the processor is to execute program code of an application that accesses the file system.

6. The computing system of claim 1 wherein the processor is to execute an application that accesses the first partition.

7. A machine readable storage medium containing kernel level driver program code that when executed by a processor causes the processor to perform a method comprising:

in a computing system comprising the processor and a memory where the memory comprises a non-volatile random access memory, the non-volatile random access memory partitioned into a first partition that is byte addressable, the non-volatile random access memory partitioned into a second partition that is block addressable, responding to a software request for a memory access operation into the second partition by translating a block address into a non volatile random access memory address.

8. The machine readable storage medium of claim 7 wherein, within the computing system, the first partition is accessed at cache line granularity.

9. The machine readable storage medium of claim 7 wherein, within the computing system, the non-volatile random access memory is coupled to a memory controller through a dual data rate memory bus.

10. The machine readable storage medium of claim 7 wherein the kernel level driver program code and the second partition are to implement a file system.

11. The machine readable storage medium of claim 10 wherein, within the computing system, the processor is to execute program code of an application that accesses the file system.

12. The machine readable storage medium of claim 7 wherein, within the computing system, the processor is to execute an application that accesses the first partition.

13. A method performed by a kernel level driver, comprising:

in a computing system comprising a processor and a memory where the memory comprises a non-volatile random access memory, the non-volatile random access memory partitioned into a first partition that is byte addressable, the non-volatile random access memory partitioned into a second partition that is block addressable, responding to a software request for a memory access operation into the second partition by translating a block address into a non volatile random access memory address.

14. The method of claim 13 further comprising accessing the first partition at cache line granularity.

15. The method of claim 13 wherein, within the computing system, the non-volatile random access memory is coupled to a memory controller through a dual data rate memory bus.

16. The method of claim 13 wherein the kernel level driver and the second partition implement a file system.

17. The method of claim 16 further comprising the processor executing program code of an application that accesses the file system.

18. The method of claim 13 further comprising the processor executing program code of an application that accesses the first partition.