Data processing device

• US 10,001,991 B2
• Filed: 02/04/2016
• Issued: 06/19/2018
• Est. Priority Date: 09/06/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ohtani, Sugako, Kondo, Hiroyuki
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US15/015,565
• Publication Number:
  US 20160154646A1
• Time in Patent Office: 866 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Claims

1. A data processing device executing a division instruction, the data processing device comprising:

an instruction decoder configured to decode an instruction code with the division instruction for operating on data, the instruction decoder further configured to determine whether the data is signed data;

a controller for determining shift width and, when the data is signed data, determining whether the data is negative signed data or positive signed data; and

an operation unit performing the arithmetic instruction for a number of cycles based on the shift width determined by the controller;

wherein the controller determines shift width and whether the data is negative signed data or positive signed data as part of execution of the division instruction by the data processing device.

2. The data processing device of claim 1, wherein the controller determines the shift width after the instruction decoder decodes the instruction code, and before the operation unit performs the division instruction.

3. The data processing device of claim 1, wherein the controller determines the shift width based on a position of a first effective bit of the data.

4. The data processing device of claim 3, wherein when the data is negative signed data, the first effective bit of the data determined by the controller has a value of “

0”

.

5. The data processing device of claim 3, wherein when the data is positive signed data, the first effective bit of the data determined by the controller has a value of “

1”

.

6. The data processing device of claim 3, wherein when the data is unsigned data, the first effective bit of the data determined by the controller has a value of “

1”

.

7. The data processing device of claim 1, wherein a larger shift width results in fewer cycles in which the operation unit performs the division instruction.

8. The data processing device of claim 1, wherein the number of cycles in which the operation unit performs the division instruction relates inversely to a size of the shift width.

9. A method for executing a division instruction in a data processing device, the method comprising the steps of:

decoding an instruction code with the division instruction for operating on data;

determining whether the data is signed data;

determining shift width;

determining, when the data is signed data, whether the data is negative signed data or positive signed data; and

performing the arithmetic instruction for a number of cycles based on the shift width;

wherein determining the shift width and determining whether the data is negative signed data or positive signed data is part of execution of the division instruction by the data processing device.

10. The method of claim 9, wherein the shift width is determined after the decoding of the instruction code, and before performing of the division instruction.

11. The method of claim 9, wherein the determination of the shift width is based on a position of a first effective bit of the data.

12. The method of claim 11, wherein when the data is negative signed data, the first effective bit of the data has a value of “

0”

.

13. The method of claim 11, wherein when the data is positive signed data, the first effective bit of the data has a value of “

1”

.

14. The method of claim 11, wherein when the data is unsigned data, the first effective bit of the data determined has a value of “

1”

.

15. The method of claim 9, wherein a larger shift width results in fewer cycles in which the division instruction is performed.

16. The method of claim 9, wherein the number of cycles in which the division instruction is performed relates inversely to a size of the shift width.

17. A data processing device executing arithmetic instructions, the data processing device comprising:

a decoder decoding instructions, including a division instruction, the division instruction including storage register information identifying a register containing a dividend value;

a controller determining a position of a first effective bit of the dividend value as part of execution of the division instruction by the data processing device; and

an operation unit performing the division instruction to calculate a quotient value, wherein a number of cycles for performing the division instruction is based on the position of the first effective bit of the dividend value.

18. The data processing device of claim 17, wherein the controller determines the position of the first effective bit of the dividend value after the decoder has decoded the division instruction, and before the operation unit calculates the quotient value.

19. The data processing device of claim 17, wherein when the dividend value stored in the register is negative signed data, the first effective bit of the dividend value determined by the controller has a value of “

0”

.

20. The data processing device of claim 17, wherein when the dividend value stored in the register is positive signed data, the first effective bit of the dividend value determined by the controller has a value of “

1”

.

21. The data processing device of claim 17, wherein when the dividend value stored in the register is unsigned data, the first effective bit of the dividend value determined by the controller has a value of “

1”

.

22. The data processing device of claim 17, wherein the controller determines a shift width for the dividend value based on the position of the first effective bit of the dividend data.

23. The data processing device of claim 17, wherein a larger shift width results in fewer cycles in which the operation unit performs the division instruction.

24. The data processing device of claim 17, wherein the number of cycles in which the operation unit performs the division instruction relates inversely to a size of the shift width.

25. A method of executing arithmetic instructions in a data processing device, the method comprising the steps of:

decoding a division instruction, the division instruction including storage register information identifying a register containing a dividend value;

determining a position of a first effective bit of the dividend value as part of execution of the division instruction; and

performing the division instruction to calculate a result, wherein a number of cycles for performing the division instruction is based on the position of the first effective bit of the dividend value.

26. The method of claim 25, wherein the position of the first effective bit of the dividend value is determined after the decoding of the division instruction, and before the result is calculated.

27. The method of claim 25, wherein when the dividend value stored in the register is negative signed data, the first effective bit of the dividend value has a value of “

0”

.

28. The method of claim 25, wherein when the dividend value stored in the register is positive signed data, the first effective bit of the dividend value has a value of “

1”

.

29. The method of claim 25, wherein when the dividend value stored in the register is unsigned data, the first effective bit of the dividend value has a value of “

1”

.

30. The method of claim 25, further comprising determining a shift width for the dividend value based on the position of the first effective bit of the dividend data.

31. The method of claim 25, wherein a larger shift width results in fewer cycles in which the division instruction is performed.

32. The method of claim 25, wherein the number of cycles in which the division instruction is performed relates inversely to a size of the shift width.

33. A data processing device executing instruction codes, the data processing device comprising:

an instruction decoder that decodes an instruction code specifying a division instruction and identifying a storage register containing a dividend value; and

a control logic unit that determines a first effective bit of the dividend value and performs the division instruction to calculate a quotient, wherein the control logic unit determines the first effective bit of the dividend value as part of the execution of the instruction code;

wherein a number of cycles for completing the instruction code specifying the division instruction is based on the determined first effective bit of the dividend value.

34. The data processing device of claim 33, wherein the control logic unit determines the first effective bit of the dividend value after the instruction decoder decodes the instruction code, and before the control logic unit performs the division instruction.

35. The data processing device of claim 33, wherein the control logic unit determines a bit shift width based on a location of a first effective bit of the dividend value.

36. The data processing device of claim 35, wherein when the dividend value is negative signed data, the first effective bit of the dividend value determined by the control logic unit has a value of “

0”

.

37. The data processing device of claim 35, wherein when the dividend value is positive signed data, the first effective bit of the dividend value determined by the control logic unit has a value of “

1”

.

38. The data processing device of claim 35, wherein when the dividend value is unsigned data, the first effective bit of the dividend value determined by the control logic unit has a value of “

1”

.

39. The data processing device of claim 35, wherein a larger bit shift width results in fewer cycles in which the division instruction is completed.

40. The data processing device of claim 35, wherein the number of cycles in which the division instruction is completed relates inversely to a size of the bit shift width.

41. A method for executing instruction codes in a data processing device, the method comprising the steps of:

decoding an instruction code specifying a division instruction;

identifying a storage register containing a dividend value;

determining a first effective bit of the dividend value; and

executing the division instruction to calculate a quotient;

wherein the determination of the first effective bit of the dividend value is part of the execution of the instruction code;

wherein a number of cycles for completing the instruction code specifying the division instruction is based on the determined first effective bit of the dividend value.

42. The method of claim 41, wherein the first effective bit of the dividend value is determined after the decoding of the instruction code, and before the division instruction is performed.

43. The method of claim 41, wherein the determination of a bit shift width is based on a location of the first effective bit of the dividend value.

44. The method of claim 43, wherein when the dividend value is negative signed data, the first effective bit of the dividend value has a value of “

0”

.

45. The method of claim 43, wherein when the dividend value is positive signed data, the first effective bit of the dividend value has a value of “

1”

.

46. The method of claim 43, wherein when the dividend value is unsigned data, the first effective bit of the dividend value has a value of “

1”

.

47. The method of claim 43, wherein a larger bit shift width results in fewer cycles in which the division instruction is completed.

48. The method of claim 43, wherein the number of cycles in which the division instruction is completed relates inversely to a size of the bit shift width.

49. A data processing device for executing instruction codes, the data processing device comprising:

an instruction decoder that decodes an instruction code, the instruction code including a division instruction and information identifying a storage register containing a dividend value; and

a control logic unit that determines a shift width based on a position of a first effective bit of the dividend value and performs the division instruction to calculate a quotient, wherein the control logic unit determines the first effective bit of the dividend as part of the execution of the instruction code;

wherein a number of cycles for completing the division instruction varies based on the determined first effective bit of the dividend value.

50. The data processing device of claim 49, wherein when the dividend value is negative signed data, the first effective bit of the dividend value determined by the controller has a value of “

0”

.

51. The data processing device of claim 49, wherein when the dividend value is positive signed data, the first effective bit of the dividend value determined by the controller has a value of “

1”

.

52. The data processing device of claim 49, wherein when the dividend value is unsigned data, the first effective bit of the dividend value determined by the controller has a value of “

1”

.

53. The data processing device of claim 49, wherein a larger shift width results in fewer cycles in which the division instruction is completed.

54. The data processing device of claim 49, wherein the number of cycles in which the division instruction is completed relates inversely to a size of the shift width.

55. A method for executing instruction codes on a data processing device, the method comprising the steps of:

decoding an instruction code, the instruction code specifying a division operation and information identifying a storage register containing a dividend value;

determining a shift width based on a position of a first effective bit of the dividend value; and

performing the division operation to calculate a quotient;

wherein the determination of the first effective bit of the dividend value is part of the execution of the instruction code by the data processing device;

wherein a number of cycles for completing execution of the division operation varies based on the determined first effective bit of the dividend value.

56. The method of claim 55, wherein when the dividend value is negative signed data, the first effective bit of the dividend value has a value of “

0”

.

57. The method of claim 55, wherein when the dividend value is positive signed data, the first effective bit of the dividend value has a value of “

1”

.

58. The method of claim 55, wherein when the dividend value is unsigned data, the first effective bit of the dividend value has a value of “

1”

.

59. The method of claim 55, wherein a larger bit shift width results in fewer cycles in which the division operation is completed.

60. The method of claim 55, wherein the number of cycles in which the division operation is completed relates inversely to a size of the bit shift width.

61. A data processing device for executing instruction codes, the data processing device comprising:

a divider circuit executing a division instruction on a dividend value for a number of cycles, the division instruction and the dividend value being included in an instruction code; and

a controller for determining a bit location of a first effective bit of the dividend value, the bit location being determined during execution of the instruction code;

wherein the number of cycles in which the divider circuit performs the division instruction is based on the determination of the bit location in the dividend value that includes the first effective bit.

62. The data processing device of claim 61, wherein when the dividend value is negative signed data, the first effective bit of the dividend value determined by the controller has a value of “

0”

.

63. The data processing device of claim 61, wherein when the dividend value is positive signed data, the first effective bit of the dividend value determined by the controller has a value of “

1”

.

64. The data processing device of claim 61, wherein when the dividend value is unsigned data, a first effective bit of the dividend value determined by the controller has a value of “

1”

.

65. The data processing device of claim 61, wherein the controller determines a shift width for the dividend value based on the bit location of the first effective bit of the dividend data.

66. The data processing device of claim 65, wherein a larger shift width results in fewer cycles in which the division instruction is performed by the divider circuit.

67. The data processing device of claim 65, wherein the number of cycles in which the division instruction is performed by the divider circuit relates inversely to a size of the shift width.

68. A method for executing instruction codes on a data processing device, the method comprising the steps of:

performing a division instruction on a dividend value for a number of cycles, the division instruction and the dividend value being included in an instruction code; and

determining a bit location of a first effective bit of the dividend value, the bit location being determined during execution of the instruction code;

wherein the number of cycles used to perform the division instruction varies based on the determined bit location in the dividend value that includes the first effective bit.

69. The method of claim 68, wherein when the dividend value is negative signed data, the first effective bit of the dividend value determined by the controller has a value of “

0”

.

70. The method of claim 68, wherein when the dividend value is positive signed data, the first effective bit of the dividend value has a value of “

1”

.

71. The method of claim 68, wherein when the dividend value is unsigned data, the first effective bit of the dividend value has a value of “

1”

.

72. The method of claim 68, further comprising determining a shift width for the dividend value based on the bit location of the first effective bit of the dividend data.

73. The method of claim 72, wherein a larger shift width results in fewer cycles in which the division instruction is performed.

74. The method of claim 72, wherein the number of cycles in which the division instruction is performed relates inversely to a size of the shift width.

75. A data processing device comprising:

a register containing a dividend value, the dividend value having effective data and uneffective data;

a divider circuit for executing an arithmetic instruction, the divider circuit executing the arithmetic instruction on the effective data of the dividend value for a number of cycles; and

a controller for determining a first bit location of the uneffective data of the dividend value;

wherein the number of cycles executed by the divider circuit to generate a quotient depends on the first bit location of the uneffective data of the dividend value.

76. The data processing device of claim 75, wherein when the dividend value includes effective data having a negative value, the first bit location of the dividend value determined by the controller has a value of “

0”

.

77. The data processing device of claim 75, wherein when the dividend value includes effective data having a positive value, the first bit location of the dividend value determined by the controller has a value of “

1”

.

78. The data processing device of claim 75, wherein when the dividend value includes unsigned data, the first bit location of the dividend value determined by the controller has a value of “

1”

.

79. The data processing device of claim 75, wherein the controller determines a shift width for the dividend value based on the first bit location of the uneffective bit of the dividend data.

80. The data processing device of claim 79, wherein a larger shift width results in fewer cycles in which the division instruction is executed by the divider circuit.

81. The data processing device of claim 79, wherein the number of cycles in which the division instruction is executed by the divider circuit relates inversely to a size of the shift width.

82. A method for executing a division instruction on a data processing device, the method comprising the steps of:

determining a first bit location of uneffective data of a dividend value, the dividend value comprising effective and uneffective data; and

executing the division instruction on the effective data of the dividend value for a number of cycles;

wherein the number of cycles executed depends on the first bit location of the uneffective data of the dividend value.

83. The method of claim 82, wherein when the dividend value includes effective data having a negative value, the first bit location of the dividend value has a value of “

0”

.

84. The method of claim 82, wherein when the dividend value includes effective data having a positive value, the first bit location of the dividend value has a value of “

1”

.

85. The method of claim 82, wherein when the dividend value includes unsigned data, the first bit location of the dividend value has a value of “

1”

.

86. The method of claim 82, further comprising determining a shift width for the dividend value based on the first bit location of the uneffective data of the dividend value.

87. The method of claim 86, wherein a larger shift width results in fewer cycles in which the division instruction is executed.

88. The method of claim 86, wherein the number of cycles in which the division instruction is executed relates inversely to a size of the shift width.

89. A data processing device executing an arithmetic instruction, the device comprising:

an instruction decoder decoding an instruction code to determine the arithmetic instruction;

a controller reading a data value and determining a bit location of at least one effective bit of the data value involved in the arithmetic instruction; and

a divider circuit performing the arithmetic instruction on effective bits of the data value;

wherein the controller determines the bit location as part of the execution of the arithmetic instruction on the data value;

wherein the operation unit executes the arithmetic instruction on effective bits of the data value based on the bit location determined by the controller;

wherein the controller determines a shift width for the dividend value based on the bit location of the at least one effective bit of the data value.

90. The data processing device of claim 89, wherein the controller determines the bit location after the instruction decoder decodes the instruction code.

91. The data processing device of claim 89, wherein the controller determines the bit location before the operation unit begins executing the arithmetic instruction on the effective bits of the data value.

92. The data processing device of claim 89, wherein the data value includes at least one uneffective bit;

wherein the operation unit only executes the arithmetic instruction on the effective bits of the data value.

93. The data processing device of claim 89, wherein the controller determines if data value is signed or unsigned.

95. The data processing device of claim 89, wherein a number of cycles in which the arithmetic instruction is executed by the operation unit relates inversely to a size of the shift width.

96. The data processing device of claim 89, wherein a larger shift width results in fewer cycles in which the operation unit executes the arithmetic instruction.

94. A data processing device executing an arithmetic instruction, the device comprising:

an instruction decoder decoding an instruction code to determine the arithmetic instruction;

a controller reading a data value and determining a bit location of at least one effective bit of the data value involved in the arithmetic instruction; and

a divider circuit performing the arithmetic instruction on effective bits of the data value;

wherein the controller determines the bit location as part of the execution of the arithmetic instruction on the data value;

wherein the operation unit executes the arithmetic instruction on effective bits of the data value based on the bit location determined by the controller;

wherein the operation unit executes the arithmetic instruction for a number of cycles based on the bit location of at least one effective bit of the data value.

117. The data processing device of claim 94, wherein the controller determines the bit location after the instruction decoder decodes the instruction code.

118. The data processing device of claim 94, wherein the controller determines the bit location before the operation unit begins executing the arithmetic instruction on the effective bits of the data value.

119. The data processing device of claim 94, wherein the data value includes at least one uneffective bit;

wherein the operation unit only executes the arithmetic instruction on the effective bits of the data value.

120. The data processing device of claim 94, wherein the controller determines if data value is signed or unsigned.

97. A method of executing an arithmetic instruction on a data value using a data processing device, the method comprising the steps of:

decoding an instruction code to determine the arithmetic instruction;

determining a bit location of at least one effective bit of the data value; and

executing the arithmetic instruction on effective bits of the data value based on the bit location of the at least one effective bit of the data value;

wherein the determination of the bit location is part of the execution of the arithmetic function on the data value;

wherein the controller determines a shift width for the dividend value based on the bit location of the at least one effective bit of the data value.

98. The method of claim 97, wherein the determination of the bit location is after the decoding of the instruction code.

99. The method of claim 97, wherein the determination of the bit location is before the performing of the arithmetic instruction on the effective bits of the data value.

100. The method of claim 97, wherein the data value includes at least one uneffective bit;

wherein the arithmetic instruction is only performed on the effective bits of the data value.

101. The method of claim 97, wherein the controller determines if data value is signed or unsigned.

103. The method of claim 97, wherein a number of cycles in which the arithmetic instruction is executed relates inversely to a size of the shift width.

104. The method claim 97, wherein a larger shift width results in fewer cycles in which the operation unit executes the arithmetic instruction.

102. A method of executing an arithmetic instruction on a data value using a data processing device, the method comprising the steps of:

decoding an instruction code to determine the arithmetic instruction;

determining a bit location of at least one effective bit of the data value; and

executing the arithmetic instruction on effective bits of the data value based on the bit location of the at least one effective bit of the data value;

wherein the determination of the bit location is part of the execution of the arithmetic function on the data value;

wherein the arithmetic instruction is executed for a number of cycles based on the bit location of the at least one effective bit of the data value.

121. The method of claim 102, wherein the determination of the bit location is after the decoding of the instruction code.

122. The method of claim 102, wherein the determination of the bit location is before the performing of the arithmetic instruction on the effective bits of the data value.

123. The method of claim 102, wherein the data value includes at least one uneffective bit;

wherein the arithmetic instruction is only performed on the effective bits of the data value.

124. The method of claim 102, wherein the controller determines if data value is signed or unsigned.

105. A data processing device executing an arithmetic instruction on a data value, the device comprising:

a decoder decoding an instruction code to determine the arithmetic instruction to be performed on the data value;

a controller determining a position of effective bits of the data value; and

a divider circuit executing the arithmetic instruction on the effective bits of the data value based on the position of the effective bits determined by the controller;

wherein the controller determines the position of effective bits of the data value as part of the execution of the arithmetic function on the data value;

wherein the divider circuit performs the arithmetic instruction for a number of cycles based on the position of at least one effective bit of the data value.

106. The data processing device of claim 105, wherein the controller determines the position of the effective bits after the decoder decodes the instruction code.

107. The data processing device of claim 105, wherein the controller determines the position of the effective bits before the divider circuit begins executing the arithmetic instruction on the effective bits of the data value.

108. The data processing device of claim 105, wherein the data value includes at least one uneffective bit and at least one effective bit;

wherein the divider circuit only performs operations of the arithmetic instruction using the effective bits of the data value.

109. The data processing device of claim 105, wherein the controller determines if data value is signed or unsigned.

110. The data processing device of claim 105, wherein the arithmetic instruction is a division instruction and the data value is a dividend of a division operation specified by the division instruction.

111. A method of executing an arithmetic instruction on a data value using a data processing device, the method comprising the steps of:

decoding an instruction code to determine the arithmetic instruction to be performed on the data value;

determining a position of effective bits of the data value; and

executing the arithmetic instruction on the effective bits of the data value based on the position of the effective bits;

wherein the determination of the position of effective bits of the data value occurs as part of the execution of the arithmetic function on the data value;

wherein the performing of the arithmetic instruction occurs for a number of cycles based on the bit location of at least one effective bit of the data value.

112. The method of claim 111, wherein the determination of the position of the effective bits is after decoding of the instruction code.

113. The method of claim 111, wherein the determination of the position of the effective bits is before executing of the arithmetic instruction on the effective bits of the data value.

114. The method of claim 111 wherein the data value includes at least one uneffective bit;

wherein operations of the arithmetic instruction are only performed using the effective bits of the data value.

115. The method of claim 111, wherein the controller determines if data value is signed or unsigned.

116. The method of claim 111, wherein the arithmetic instruction is a division instruction and the data value is a dividend of a division operation specified by the division instruction.