USB interface detector

• US 10,002,061 B2
• Filed: 05/20/2016
• Issued: 06/19/2018
• Est. Priority Date: 05/22/2015
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Chen, Jianli, Sun, Weiming, Wang, Emma, Huang, Lei
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): Dang, Phong H
• Application Number:
  US15/160,085
• Publication Number:
  US 20160342492A1
• Time in Patent Office: 760 Days
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]

Abstract

Systems and methods are disclosed, including a USB interface detector, a detection method, a USB connector, and an electronic device. The detection method may be applicable to the USB connector mounted in the electronic device. According to an operation mode of the electronic device, a first pin and a second pin in the USB interface can be pulled up or pulled down. After the pull up or the pull down, a voltage change at the first and second pins are detected. If the voltage changes cross a reference voltage, an instruction related to attachment or detachment with a second device can be provided.

Claims

1. A universal serial bus (USB) interface detection method, applicable to a USB connector mounted in a first device, the method comprising:

pulling up a voltage of a first pin and a voltage of a second pin in the USB connector in a downstream facing port (DFP) operation mode to be higher than a first reference voltage using a terminating circuit;

enabling a first comparator and a second comparator during a first phase, the first phase including;

comparing the voltage of the first pin with the first reference voltage using the first comparator;

comparing the voltage of the second pin with the first reference voltage using the second comparator;

enabling a third comparator and a fourth comparator during a second phase in response to at least one of the voltage of the first pin or the voltage of the second pin being less than the first reference voltage, the second phase including;

comparing each of the voltage of the first pin and the voltage of the second pin to a second reference voltage and a third reference voltage using the first comparator, the second comparator, the third comparator, and the fourth comparator; and

providing, at an output terminal, an instruction related to attachment or detachment of the first device with a second device based on an output of the first comparator, an output of the second comparator, an output of the third comparator, and an output of the fourth comparator during the second phase.

2. The method of claim 1, wherein the third reference voltage is lower than the second reference voltage, and the second reference voltage is lower than the first reference voltage.

8. The method of claim 1, wherein the second phase includes:

comparing the voltage of the first pin to the second reference voltage using the first comparator;

comparing the voltage of the first pin to the third reference voltage using the second comparator;

comparing the voltage of the second pin to the second reference voltage using the third comparator; and

comparing the voltage of the second pin to the third reference voltage using the fourth comparator.

9. The method of claim 1, wherein the providing the instruction includes:

providing an instruction related to attachment of the first device with an upstream facing port (UFP) and a first attachment orientation in response to the voltage of the first pin being greater than the second reference voltage, the voltage of the second pin being greater than the third reference voltage, and the voltage of the second pin being less than the second reference voltage.

10. The method of claim 9, wherein the providing the instruction includes:

providing an instruction related to attachment of the first device with the UFP and a second attachment orientation in response to the voltage of the second pin being greater than the second reference voltage, the voltage of the first pin being greater than the third reference voltage, and the voltage of the first pin being less than the second reference voltage.

11. The method of claim 1, wherein the providing the instruction includes:

providing an instruction related to attachment with a debugging accessory in response to the voltage of the first pin being greater than the third reference voltage but less than the second reference voltage, and the voltage of the second pin being greater than the third reference voltage but less than the second reference voltage.

12. The method of claim 1, wherein the providing the instruction includes:

providing an instruction related to attachment with an audio adapter accessory in response to the voltage of the first pin being less than the third reference voltage, and the voltage of the second pin being less than the third reference voltage.

13. The method of claim 1, wherein the third comparator and the fourth comparator are disabled during the first phase.

3. A universal serial bus (USB) interface detector, applicable to a USB connector mounted in a first device, comprising:

a first detection terminal and a second detection terminal, respectively connected to a first pin and a second pin of the USB connector;

a terminating circuit configured to pull up a voltage of the first pin and a voltage of the second pin in a downstream facing port (DFP) operation mode and to pull down the voltage of the first pin and the voltage of the second pin in an upstream facing port (UFP) operation mode;

a comparator circuit including a plurality of comparators operable during a first phase and a second phase, the plurality of comparators including a first comparator, a second comparator, a third comparator, and a fourth comparator, each of the plurality of comparators selectively coupled to either the first pin or the second pin, each of the plurality of comparators being coupled to a different reference voltage, at least one of the plurality of comparators being disabled during the first phase,

wherein, during the first phase, the first comparator is configured to compare the voltage of the first pin to a first reference voltage, and the second comparator is configured to compare the voltage of the second pin to the first reference voltage,

wherein, during the second phase, each of the first comparator, the second comparator, the third comparator, and the fourth comparator is configured to compare the voltage of the first pin or the second pin to a different reference voltage;

a selection circuit configured to selectively couple the first pin or the second pin to each of the plurality of comparators; and

a digital control circuit coupled to outputs of the plurality of comparators, the digital control circuit configured to receive an instruction based on results of comparisons performed by the plurality of comparators.

4. The USB interface detector of claim 3, wherein the instruction refers to an instruction related to attachment or detachment with a second device.

5. The USB interface detector of claim 3, wherein the comparator circuit is configured to provide, according to comparison results during the second phase, an instruction related to a type of a second device or an instruction related to a magnitude of a provided charging current.

6. The USB interface detector of claim 3, wherein the digital control circuit configured to:

control the terminating circuit to pull up or pull down the first and second pins according to an operation mode of the first device;

provide a selection signal to the selection circuit;

provide a respective enable signal to each of the plurality of comparators during the second phase; and

set the respective reference voltage of the plurality of comparators of the comparator circuit.

7. The USB interface detector of claim 3, wherein the terminating circuit is configured to:

provide a pull-up current source for the first and second detection terminals when the first device is in a DFP operation mode; and

connect the first and second detection terminals to a pull-down resistor when the first device is in a UFP operation mode.

14. A universal serial bus (USB) interface detection method, applicable to a USB connector mounted in a first device, the method comprising:

pulling down a voltage of a first pin and a voltage of a second pin in the USB connector in an upstream facing port (UFP) operation mode to be lower than a first reference voltage using a terminating circuit;

enabling a first comparator and a second comparator during a first phase, the first phase including;

comparing the voltage of the first pin with the first reference voltage using the first comparator;

comparing the voltage of the second pin with the first reference voltage using the second comparator;

enabling a third comparator and a fourth comparator during a second phase in response to at least one of the voltage of the first pin or the voltage of the second pin being greater than the first reference voltage, the second phase including;

comparing the voltage of the first pin to each of a plurality of reference voltages using the first comparator, the second comparator, the third comparator, and the fourth comparator; and

providing, at an output terminal, an instruction related to related to a magnitude of a provided charging current based on an output of the first comparator, an output of the second comparator, an output of the third comparator, and an output of the fourth comparator during the second phase.

15. The method of claim 14, wherein the plurality of reference voltages in the second phase include a second reference voltage, a third reference voltage, a fourth reference voltage, and a fifth reference voltage.

16. The method of claim 15, wherein the second phase includes:

comparing the voltage of the first pin to the second reference voltage using the first comparator;

comparing the voltage of the first pin to the third reference voltage using the second comparator;

comparing the voltage of the first pin to the fourth reference voltage using the third comparator; and

comparing the voltage of the first pin to the fifth reference voltage using the fourth comparator.

17. The method of claim 14, wherein the third comparator and the fourth comparator are disabled during the first phase.