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Memory cell structure of magnetic memory with spin device elements

  • US 10,002,655 B2
  • Filed: 12/13/2016
  • Issued: 06/19/2018
  • Est. Priority Date: 04/01/2015
  • Status: Active Grant
First Claim
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1. A magnetic memory, comprising:

  • a memory cell configured to store a one-bit data; and

    a data identification circuit,wherein the memory cell includes;

    a first bias node;

    a second bias node;

    a connection node;

    a first spin device element connected between the first bias node and the connection node; and

    a second spin device element connected between the connection node and the second bias node,wherein the first spin device element includes;

    a first recording layer having a first reversible magnetization;

    a first reference layer having a first fixed magnetization; and

    a first spacer layer provided between the first recording layer and the first reference layer,wherein the second spin device element includes;

    a second recording layer having a second reversible magnetization;

    a second reference layer having a second fixed magnetization; and

    a second spacer layer provided between the second recording layer and the second reference layer,wherein the first recording layer and the second recording layer are connected to each other via the connection node,wherein the first reference layer is connected to the first bias node,wherein the second reference layer is connected to the second bias node,wherein the first fixed magnetization of the first reference layer and the second fixed magnetization of the second reference layer are directed in a same direction,wherein the magnetizations of the first recording layer and the second recording layer are directed in opposite directions,wherein, in data reading, a bias voltage is applied between the first bias node and the second bias node across the first and second spin device elements to allow a read current to flow between the first bias node and the second bias node through the first and second spin device elements, andwherein the data identification circuit is configured to identify the one-bit data stored in the memory cell based on a voltage generated on the connection node.

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