Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

• US 10,002,791 B1
• Filed: 04/06/2017
• Issued: 06/19/2018
• Est. Priority Date: 04/06/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bao, Ruqiang, Jagannathan, Hemanth, Jamison, Paul C., Lee, ChoongHyun
• Primary Examiner(s): Tran, Tran
• Application Number:
  US15/481,012
• Time in Patent Office: 439 Days
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

Claims

1. A method for forming a device having multiple field effect transistors (FETs) with each FET having a different work function gate stack, the method comprising:

forming first, second, third, and fourth FETs over a semiconductor substrate;

forming an interfacial layer and a high-k dielectric layer over the first, second, third, and fourth FETs;

forming a first work function conducting layer over the high-k dielectric layer;

removing the first work function conducting layer from the third FET;

depositing a second work function conducting layer;

removing the first and second work function conducting layers from the second FET;

depositing a third work function conducting layer;

removing the first, second, and third work function conducting layers from the first FET;

depositing a fourth work function conducting layer;

depositing a sacrificial block layer and a sacrificial cap layer;

removing the sacrificial block layer and the sacrificial cap layer from the first and second FETs;

depositing a fifth work function conducting layer and a patterning cap layer;

removing the patterning cap layer, the fifth work function conducting layer, and the sacrificial cap layer from the third and fourth FETs;

removing the sacrificial block layer from the third and fourth FETs;

depositing first and second conducting layers over the first, second, third, and fourth FETs;

depositing a dummy fill material;

recessing the dummy fill material;

recessing remaining work function conducting layers from the first, second, third, and fourth FETs to expose a hard mask of each of the first, second, third, and fourth FETs;

stripping the dummy fill material;

depositing a dielectric layer up to a top surface of the hard mask of each of the first, second, third, and fourth FETs;

recessing the dielectric layer and forming spacers;

performing isolation patterning of the first, second, third, and fourth FETs for isolation FETs;

depositing an insulator between the recesses formed by the isolation patterning; and

etching to expose a top portion of a channel of each of the first, second, third, and fourth FETs.

2. The method of claim 1, wherein the first, second, third, and fourth work function conducting layers are titanium nitride (TiN) layers.

3. The method of claim 1, wherein the fifth work function conducting layer is an nFET work function metal.

4. The method of claim 3, wherein the nFET work function metal is one of titanium(Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or any combination of Ti and Al alloys.

5. The method of claim 1, wherein the patterning cap layer is a TiN layer.

6. The method of claim 1, wherein the first conducting layer is a scavenging metal or metal alloy and the second conducting layer is metal nitride, metal carbide or pure metals.

7. The method of claim 6, wherein a scavenging metal or metal alloy is one of titanium(Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or any combination of Ti and Al alloys;

wherein the metal nitride is TiN, AlN;

wherein the metal carbide is TiC, WC, AlC, TaC; and

wherein the pure metal is Co, Al, Ti, Ru, and W.

8. The method of claim 1, wherein the dummy fill material is an organic planarization layer (OPL).

9. The method of claim 1, further comprising forming source/drain regions over the channel of each of the first, second, third, and fourth FETs and further comprising forming contacts to each of the source/drain regions over each channel.

10. The method of claim 1, wherein a difference in thickness between the first, second, third, fourth, and fifth work function conducting layers is less than 2 nm.