Semiconductor integrated circuit device

• US 10,002,832 B2
• Filed: 04/21/2017
• Issued: 06/19/2018
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Matsui, Tooru, Yoshimura, Masahiro
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US15/493,338
• Publication Number:
  US 20170221825A1
• Time in Patent Office: 424 Days
• Field of Search: None
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

Claims

1. A semiconductor integrated circuit device comprising:

at least two I/O cell rows each including a plurality of I/O cells arranged in a first direction;

a plurality of external connection pads; and

a common power supply interconnect that connects together a plurality of first I/O cells configured either as I/O cells for supplying a power supply potential or as I/O cells for supplying a ground potential, the first I/O cells each included in a respective one of the at least two I/O cell rows, wherein

the first I/O cells connected together via the common power supply interconnect are arranged so as to overlap with each other in the first direction, and

the common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to a first pad which is one of the plurality of external connection pads and is located closest to the common power supply interconnect in the first direction among the plurality of external connection pads.

2. The semiconductor integrated circuit device of claim 1, wherein

the first I/O cells have a same dimension and are arranged at a same position in the first direction.

3. The semiconductor integrated circuit device of claim 1, wherein

at least one of the at least two I/O cell rows extends in a ring or frame shape entirely along a periphery of the semiconductor integrated circuit device.

4. The semiconductor integrated circuit device of claim 1, wherein

the common power supply interconnect is connected to at least two of the plurality of external connection pads, where the at least two of the plurality of external connection pads include the first pad.

5. The semiconductor integrated circuit device of claim 1, wherein

the common power supply interconnect overlaps with the first pad in a plan view.

6. A semiconductor integrated circuit device comprising:

first and second I/O cell rows each including a plurality of I/O cells arranged in a first direction; and

an internal logic circuit arranged between the first and second I/O cell rows, wherein

in the semiconductor integrated circuit device, the first I/O cell row is arranged inwardly from the internal logic circuit, and the second I/O cell row is arranged outwardly from the internal logic circuit,

the I/O cells in the first and second I/O cell rows each include a high power supply voltage region and a low supply voltage region which are separated from each other in a second direction perpendicular to the first direction, and are arranged such that each low power supply voltage region is located closer to the internal logic circuit,

the first I/O cell row includes at least one first I/O cell which is configured as an I/O cell for inputting and outputting a signal and which has a signal terminal in the low power supply voltage region of the first I/O cell, and

the signal terminal of the first I/O cell is connected to the internal logic circuit via a signal interconnect.

7. The semiconductor integrated circuit device of claim 6, wherein

the second I/O cell row includes at least one second I/O cell which is configured as an I/O cell for inputting and outputting a signal and which has a signal terminal in the low power supply voltage region of the second I/O cell, and

the signal terminal of the second I/O cell is connected to the internal logic circuit via a signal interconnect.