3D semiconductor structure and device

• US 10,002,865 B2
• Filed: 04/08/2017
• Issued: 06/19/2018
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): Crawford, Jason M
• Application Number:
  US15/482,761
• Publication Number:
  US 20170301667A1
• Time in Patent Office: 437 Days
• Field of Search: 326 37- 41, 326 47
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H03K 19/096 : Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 19/17728 : Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1774 : for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/1776 : for memories
• CPC Class Codes: H03K 3/0375 : provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.

Claims

1. A 3D structure, the structure comprising:

a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,

wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,

wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line,

wherein said second stratum comprises memory control circuits directly connected to said bit-lines and said word-lines,

wherein said second stratum comprises a first layer comprising first transistors and a second layer comprising second transistors,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

2. The 3D structure according to claim 1,

wherein said 3D structure is designed such that it could be processed to form a first 3D device and a second 3D device,

wherein said first 3D device comprises many more memory cells than said second 3D device.

3. The 3D structure according to claim 1,

wherein said 3D structure is designed to perform self-test and repair partly by activating a built-in redundancy.

4. The 3D structure according to claim 1,

wherein said second stratum is connected with a face to face connection to said first stratum.

5. The 3D structure according to claim 1, further comprising:

a wireless connection channel to at least one external device.

6. The 3D structure according to claim 1,

wherein said first bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

7. The 3D structure according to claim 1, further comprising:

vias,

wherein said directly connected comprises said vias, and

wherein said vias have a radius of less than 400 nm.

8. A 3D structure, the structure comprising:

a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,

wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,

wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line,

wherein said second stratum comprises memory control circuits directly connected to control said memory cells,

wherein said second stratum comprises a first layer comprising first transistors and a second layer comprising second transistors,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units,

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units,

wherein said 3D structure is designed such that it could be processed to form a first 3D device and a second 3D device, and

wherein said first 3D device comprises many more memory cells than said second 3D device.

9. The 3D structure according to claim 8,

wherein said 3D structure is designed to perform self-test and repair partly by activating a built-in redundancy.

10. The 3D structure according to claim 8,

wherein said second stratum is connected with a face to face connection to said first stratum.

11. The 3D structure according to claim 8, further comprising:

a wireless connection channel to at least one external device.

12. The 3D structure according to claim 8,

wherein said first stratum comprises a layer select to support selecting said first stratum.

13. The 3D structure according to claim 8, further comprising:

vias,

wherein said directly connected comprises said vias, and

wherein said vias have a radius of less than 400 nm.

14. The 3D structure according to claim 8,

wherein said first bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

15. A 3D structure, the structure comprising:

a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,

wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,

wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line,

wherein said second stratum comprises memory control circuits directly connected to control said memory cells,

wherein said second stratum comprises a first layer comprising first transistors and a second layer comprising second transistors,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units, and

wherein said 3D structure is designed to perform self-test and repair itself partly by activating a built-in redundancy.

16. The 3D structure according to claim 15,

wherein said first bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

17. The 3D structure according to claim 15,

wherein said second stratum is connected with a face to face connection to said first stratum.

18. The 3D structure according to claim 15, further comprising:

a wireless connection channel to at least one external device.

19. The 3D structure according to claim 15,

wherein said first stratum comprises a layer select to support selecting said first stratum.

20. The 3D structure according to claim 15, further comprising:

vias,

wherein said directly connected comprises said vias, and

wherein said vias have a radius of less than 400 nm.