Semiconductor device and electronic device

• US 10,002,888 B2
• Filed: 08/01/2017
• Issued: 06/19/2018
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Umezaki, Atsushi, Yamazaki, Shunpei
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/665,701
• Publication Number:
  US 20180040634A1
• Time in Patent Office: 322 Days
• Field of Search: 257438
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1334 based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
• CPC Class Codes: G02F 1/13345 Network or three-dimensional gels
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

Claims

1. A semiconductor device comprising:

a first transistor; and

a second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein the first transistor comprises a gate electrode layer, a gate insulating layer over the gate electrode layer, a first oxide semiconductor layer over the gate insulating layer and a second oxide semiconductor layer over the first oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga and Zn, and

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal.

2. The semiconductor device according to claim 1,

wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line.

3. The semiconductor device according to claim 1,

wherein sum of thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is 3 nm to 50 nm.

4. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein the first transistor comprises a gate electrode layer, a gate insulating layer over the gate electrode layer, a first oxide semiconductor layer over the gate insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer over the second oxide semiconductor layer and a drain electrode layer over the second oxide semiconductor layer,

wherein a first insulating layer is over the source electrode layer, the drain electrode layer and the second oxide semiconductor layer,

wherein a second insulating layer is over the first insulating layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga and Zn,

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal,

wherein the first insulating layer comprises oxygen and silicon,

wherein the second insulating layer comprises nitrogen and silicon,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a fourth wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor, and

wherein a gate of the fourth transistor is electrically connected to the fourth wiring.

5. The semiconductor device according to claim 4,

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring, and

wherein a gate of the third transistor is electrically connected to the fifth wiring.

6. The semiconductor device according to claim 4,

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring, and

wherein a gate of the third transistor is electrically connected to a sixth wiring.

7. The semiconductor device according to claim 4,

wherein a channel width of the first transistor is larger than a channel width of the second transistor,

wherein the channel width of the first transistor is larger than a channel width of the third transistor, and

wherein the channel width of the second transistor is larger than a channel width of the fourth transistor.

8. A semiconductor device comprising:

a first transistor; and

a second transistor,

wherein the first transistor comprises a gate electrode layer, a gate insulating layer over the gate electrode layer, a first oxide semiconductor layer over the gate insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer over the second oxide semiconductor layer and a drain electrode layer over the second oxide semiconductor layer,

wherein a first insulating layer is over the source electrode layer, the drain electrode layer and the second oxide semiconductor layer,

wherein a second insulating layer is over the first insulating layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga and Zn,

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal,

wherein the first insulating layer comprises oxygen and silicon,

wherein the second insulating layer comprises nitrogen and silicon, and

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor.

9. The semiconductor device according to claim 8,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring, and

wherein a gate of the second transistor is electrically connected to the third wiring.

10. The semiconductor device according to claim 8,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring, and

wherein a gate of the second transistor is electrically connected to a fourth wiring.