Logic circuit and semiconductor device

• US 10,002,891 B2
• Filed: 03/27/2017
• Issued: 06/19/2018
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Tsubuku, Masashi, Noda, Kosei
• Primary Examiner(s): White, Dylan
• Application Number:
  US15/469,888
• Publication Number:
  US 20170200748A1
• Time in Patent Office: 449 Days
• Field of Search: 257 71
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/161 : in field-effect transistor switches
• CPC Class Codes: H03K 19/00315 : in field-effect transistor circuits
• CPC Class Codes: H03K 19/096 : Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

Exemplary semiconductor devices include eight transistors and two capacitors interconnected in specific configurations. A display device may include a driver circuit having such a semiconductor device. An electronic device may also include such a semiconductor device and an input unit, LED lamp or speaker.

Claims

1. A semiconductor device comprising:

first to eighth transistors; and

first and second capacitors,

wherein each of the first to eighth transistors includes an oxide semiconductor layer containing indium, gallium, and zinc as a semiconductor layer,

wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is electrically connected to a gate of the second transistor,

wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is electrically connected to the other of source and drain of the first transistor,

wherein one of source and drain of the fifth transistor is electrically connected to one of source and drain of the sixth transistor,

wherein one of source and drain of the seventh transistor is electrically connected to a gate of the fifth transistor,

wherein one of source and drain of the eighth transistor is electrically connected to a gate of the sixth transistor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the fifth transistor,

wherein a second electrode of the second capacitor is electrically connected to the one of source and drain of the fifth transistor,

wherein a power supply line is electrically connected to the other of source and drain of the second transistor,

wherein the power supply line is electrically connected to the other of source and drain of the sixth transistor,

wherein a first signal is output from the one of source and drain of the first transistor,

wherein a second signal is output from the one of source and drain of the fifth transistor,

wherein a third signal is input to the other of source and drain of the third transistor and the other of source and drain of the eighth transistor, and

wherein a fourth signal is input to the other of source and drain of the fourth transistor and the other of source and drain of the seventh transistor.

2. The semiconductor device according to claim 1,

wherein each of the first to eighth transistors is a bottom gate structure.

3. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 1; and

a pixel electrically connected to the driver circuit.

4. An electronic device comprising:

the semiconductor device according to claim 1; and

an input unit or a speaker.

5. A semiconductor device comprising:

first to eighth transistors; and

first and second capacitors,

wherein each of the first to eighth transistors includes an oxide semiconductor layer containing indium, gallium, and zinc as a semiconductor layer,

wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is electrically connected to a gate of the second transistor,

wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor,

wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is electrically connected to the other of source and drain of the first transistor,

wherein one of source and drain of the fifth transistor is electrically connected to one of source and drain of the sixth transistor,

wherein one of source and drain of the seventh transistor is electrically connected to a gate of the fifth transistor,

wherein one of source and drain of the eighth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the seventh transistor is electrically connected to a gate of the eighth transistor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the fifth transistor,

wherein a second electrode of the second capacitor is electrically connected to the one of source and drain of the fifth transistor,

wherein a power supply line is electrically connected to the other of source and drain of the second transistor,

wherein the power supply line is electrically connected to the other of source and drain of the sixth transistor,

wherein a first signal is output from the one of source and drain of the first transistor,

wherein a second signal is output from the one of source and drain of the fifth transistor,

wherein a third signal is input to the other of source and drain of the third transistor and the other of source and drain of the eighth transistor, and

wherein a fourth signal is input to the other of source and drain of the fourth transistor and the other of source and drain of the seventh transistor.

6. The semiconductor device according to claim 5,

wherein each of the first to eighth transistors is a bottom gate structure.

7. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 5; and

a pixel electrically connected to the driver circuit.

8. An electronic device comprising:

the semiconductor device according to claim 5; and

an input unit or a speaker.

9. A semiconductor device comprising:

first to eighth transistors; and

first and second capacitors,

wherein each of the first to eighth transistors includes an oxide semiconductor layer containing indium, gallium, and zinc as a semiconductor layer,

wherein one of source and drain of the first transistor is directly connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is directly connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is directly connected to a gate of the second transistor,

wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to the other of source and drain of the first transistor,

wherein one of source and drain of the fifth transistor is directly connected to one of source and drain of the sixth transistor,

wherein one of source and drain of the seventh transistor is directly connected to a gate of the fifth transistor,

wherein one of source and drain of the eighth transistor is directly connected to a gate of the sixth transistor,

wherein a first electrode of the second capacitor is directly connected to the gate of the fifth transistor,

wherein a second electrode of the second capacitor is directly connected to the one of source and drain of the fifth transistor,

wherein a power supply line is directly connected to the other of source and drain of the second transistor,

wherein the power supply line is directly connected to the other of source and drain of the sixth transistor,

wherein a first signal is output from the one of source and drain of the first transistor,

wherein a second signal is output from the one of source and drain of the fifth transistor,

wherein a third signal is input to the other of source and drain of the third transistor and the other of source and drain of the eighth transistor, and

wherein a fourth signal is input to the other of source and drain of the fourth transistor and the other of source and drain of the seventh transistor.

10. The semiconductor device according to claim 9,

wherein each of the first to eighth transistors is a bottom gate structure.

11. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 9; and

a pixel electrically connected to the driver circuit.

12. An electronic device comprising:

the semiconductor device according to claim 9; and

an input unit or a speaker.

13. A semiconductor device comprising:

first to eighth transistors; and

first and second capacitor,

wherein each of the first to eighth transistors includes an oxide semiconductor layer containing indium, gallium, and zinc as a semiconductor layer,

wherein one of source and drain of the first transistor is directly connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is directly connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is directly connected to a gate of the second transistor,

wherein a gate of the third transistor is directly connected to a gate of the fourth transistor,

wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to the other of source and drain of the first transistor,

wherein one of source and drain of the fifth transistor is directly connected to one of source and drain of the sixth transistor,

wherein one of source and drain of the seventh transistor is directly connected to a gate of the fifth transistor,

wherein one of source and drain of the eighth transistor is directly connected to a gate of the sixth transistor,

wherein a gate of the seventh transistor is directly connected to a gate of the eighth transistor,

wherein a first electrode of the second capacitor is directly connected to the gate of the fifth transistor,

wherein a second electrode of the second capacitor is directly connected to the one of source and drain of the fifth transistor,

wherein a power supply line is directly connected to the other of source and drain of the second transistor,

wherein the power supply line is directly connected to the other of source and drain of the sixth transistor,

wherein a first signal is output from the one of source and drain of the first transistor,

wherein a second signal is output from the one of source and drain of the fifth transistor,

wherein a third signal is input to the other of source and drain of the third transistor and the other of source and drain of the eighth transistor, and

wherein a fourth signal is input to the other of source and drain of the fourth transistor and the other of source and drain of the seventh transistor.

14. The semiconductor device according to claim 13,

wherein each of the first to eighth transistors is a bottom gate structure.

15. A display device comprising:

a driver circuit comprising the semiconductor device according to claim 13; and

a pixel electrically connected to the driver circuit.

16. An electronic device comprising:

the semiconductor device according to claim 13; and

an input unit or a speaker.