Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes

• US 10,002,900 B2
• Filed: 07/21/2017
• Issued: 06/19/2018
• Est. Priority Date: 05/06/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kumar, Arvind, Lamorey, Mark
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US15/656,402
• Publication Number:
  US 20170323920A1
• Time in Patent Office: 333 Days
• Field of Search: 156 64, 438 67
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H05K 999/99 dummy group

Abstract

A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.

Claims

1. A method for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, the method comprising:

selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer;

manufacturing the second wafer in accordance with the selected periodicity;

placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer; and

stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer,

wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.

2. The method of claim 1, wherein said stacking step comprises:

bonding the first wafer face down onto a temporary carrier;

flipping and bonding the second wafer to the first wafer to form a wafer-to-wafer bonding;

removing the temporary carrier; and

flipping, singulating, and packaging the wafer-to-wafer bonding.

3. The method of claim 2, wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

4. The method of claim 2, wherein said bonding step bonds the first wafer face down onto the temporary carrier using a temporary adhesive, and said removing step comprises removing the temporary adhesive.

5. The method of claim 2, wherein a back face of the first wafer is bonded to a front face of the second wafer.

6. The method of claim 1, wherein said stacking step comprises:

bonding the first wafer to the second wafer in a face-to-face configuration to form a wafer-to-wafer bonding; and

flipping, singulating, and packaging the wafer-to-wafer bonding.

7. The method of claim 6, wherein said stacking step further comprises, in between said bonding step and said flipping step, thinning the first wafer using the second wafer as a handle to produce a thin first wafer in the wafer-to-wafer bonding.

8. The method of claim 6, wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

9. The method of claim 1, wherein said placing step is performed to meet a pattern density requirement imposed on the second wafer.

10. The method of claim 1, further comprising forming a Through-Silicon via connecting a portion of the first wafer to a portion of the second wafer.

11. The method of claim 1, wherein said stacking step comprises selectively bonding the first wafer to the second wafer face-to-face or back-to-face.

12. The method of claim 1, further comprising thinning the first wafer to form a thin first wafer used for said stacking step.

13. A non-transitory computer readable storage medium comprising a computer readable program for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer;

manufacturing the second wafer in accordance with the selected periodicity;

placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer; and

stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer

wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.

14. The non-transitory computer readable storage medium of claim 13, wherein said stacking step comprises:

bonding the first wafer face down onto a temporary carrier;

flipping and bonding the second wafer to the first wafer to form a wafer-to-wafer bonding;

removing the temporary carrier; and

flipping, singulating, and packaging the wafer-to-wafer bonding.

15. The non-transitory computer readable storage medium of claim 14, wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

16. The non-transitory computer readable storage medium of claim 13, wherein said stacking step comprises:

bonding the first wafer to the second wafer in a face-to-face configuration to form a wafer-to-wafer bonding; and

flipping, singulating, and packaging the wafer-to-wafer bonding.

17. The non-transitory computer readable storage medium of claim 16, wherein said stacking step further comprises, in between said bonding step and said flipping step, thinning the first wafer using the second wafer as a handle to produce a thin first wafer in the wafer-to-wafer bonding.

18. The non-transitory computer readable storage medium of claim 16, wherein the first wafer comprises a plurality of dies, and the second wafer comprises another plurality of dies, and wherein said bonding step bonds the pluralities of dies in parallel.

19. The non-transitory computer readable storage medium of claim 13, further comprising forming a Through-Silicon via connecting a portion of the first wafer to a portion of the second wafer.