Manufacturable RGB display based on thin film gallium and nitrogen containing light emitting diodes

• US 10,002,928 B1
• Filed: 04/05/2017
• Issued: 06/19/2018
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Kyocera SLD Laser Incorporated (Kyocera Corporation)
• Original Assignee: Soraa Laser Diode, Inc. (Kyocera Corporation)
• Inventors: Raring, James W., McLaurin, Melvin, Sztein, Alexander, Hsu, Po Shan
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Mustapha, Abdulfattah
• Application Number:
  US15/480,239
• Time in Patent Office: 440 Days
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/8389 using an inorganic non metallic glass type adhesive, e.g. solder glass
• CPC Class Codes: H01L 2224/83895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/83896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 27/0605 : integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/085 : including field-effect components only
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 : Multistep manufacturing methods
• CPC Class Codes: H01L 27/15 : including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/1066 : Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 29/205 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/432 : Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66136 : PN junction diodes
• CPC Class Codes: H01L 29/66143 : Schottky diodes
• CPC Class Codes: H01L 29/66318 : Heterojunction transistors
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 : with a PN heterojunction gate
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/8613 : Mesa PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 33/0025 : comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/0066 : with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0075 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01S 5/0203 : Etching
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: H01S 5/227 : Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

providing a gallium and nitrogen containing substrate having a surface region;

forming a gallium and nitrogen containing epitaxial material overlying the surface region, the epitaxial material comprising a release material overlying the gallium and nitrogen containing substrate and at least an intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material or at least an n-type gallium and nitrogen containing region overlying the release material or at least a p-type gallium and nitrogen containing region overlying the release material or at least a combination of one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material;

patterning the epitaxial material and forming mesas to form a plurality of dice arranged in an array, each die corresponding to at least one semiconductor device and being arranged by a first pitch between adjacent die in the array;

forming an interface region overlying the epitaxial material, the interface region comprising a metal, a semiconductor, a dielectric, oxide, glass, or a polymer;

subjecting the release material to an energy source to fully or partially remove the release material, the release material disposed between the surface region and the one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region, wherein fully or partially removing the release material leaves undercuts between the surface region and the one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region;

bonding the interface region to a carrier wafer to form a bonded structure, while maintaining the release material completely or partially removed from the bonded structure, wherein subjecting the release material to the energy source is performed prior to the bonding step;

releasing the plurality of dice provided on the gallium and nitrogen containing substrate member to transfer a plurality of dice to one or more carrier wafers wherein each pair of the transferred dice is configured with a second pitch between each pair of dice on a carrier wafer, wherein the second pitch is larger than the first pitch;

processing at least one of the plurality of dice to form at least the semiconductor device.

2. The method of claim 1 whereupon the carrier wafer has a larger diameter and/or a larger total surface area than the gallium and nitrogen containing substrate;

wherein the plurality of dice are processed on the carrier wafer.

3. The method of claim 1 further comprising transferring one or more additional dice from another substrate to the carrier wafer, wherein each of the one or more carrier wafers has a larger diameter than a diameter of the gallium and nitrogen containing substrate.

4. The method of claim 1, wherein the carrier wafer is selected from a sapphire wafer, silicon carbide wafer, aluminum nitride wafer, silicon wafer, gallium arsenide wafer, diamond wafer, gallium nitride wafer, or an indium phosphide wafer.

5. The method of claim 1, wherein the release material is selected from GaN, InGaN, AlInGaN, or AlGaN.

6. The method of claim 1, wherein the energy source includes a PEC etch that comprises KOH or any of its species.

7. The method of claim 1, wherein the energy source is a PEC etch;

wherein the PEC etch selectively removes the release region while leaving an anchor region in tact to support a respective die before bonding the interface region to the carrier wafer, and the anchor region separates after the bonding;

wherein the anchor region is comprised of metal, semiconductor, dielectric, oxide, polymer, or a combination thereof.

8. The method of claim 1, wherein the energy source is a PEC etch;

wherein the PEC etch selectively removes the release region while leaving a metal anchor region in tact to support a respective die before bonding the interface region to the carrier wafer, and the metal anchor region separates after the bonding;

wherein the metal anchor region is configured to provide an electrical short between an anode region and a cathode region to further facilitate the PEC etch.

9. The method of claim 1, wherein the bonding comprising thermal bonding, plasma activated bonding, anodic bonding, chemical bonding, or combinations thereof wherein the surface region of the gallium and nitrogen containing substrate is configured in a polar, semipolar, or non-polar orientation;

wherein the interface region is bonded to the carrier wafer using at least one of a metal-metal pair, dielectric-dielectric, oxide-oxide, semiconductor-semiconductor, glass such as spin-on-glass, soldering alloys, polymers, photoresists, wax, or a combination thereof.

10. The method of claim 1, wherein the substrate is reclaimed and prepared for reuse after transferring each of the plurality of dice to one or more carrier wafers.

11. The method of claim 1, wherein each of the die comprises one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a light emitting region, a current spreading region, an optical cladding region, a drift region, an edge termination region, an emitter region, a base region, a collector region, a gate region, an isolation region, or a passivation region either alone or in any combination.

12. The method of claim 1, wherein the semiconductor device is an LED device.

13. The method of claim 1, wherein the semiconductor device is laser diode device.

14. The method of claim 1, wherein the semiconductor device is a Schottky diode power electronic device.

15. The method of claim 1, wherein the semiconductor device is a p-n diode power electronic device.

16. The method of claim 1, wherein the semiconductor device is a bipolar junction transistor power electronic device.

17. The method of claim 1, wherein the semiconductor device is a high electron mobility transistor power electronic device.

18. The method of claim 1, wherein the semiconductor device is a field effect transistor power electronic device.

19. The method of claim 1, wherein the semiconductor device is a heterojunction bipolar transistor device.

20. The method of claim 1, wherein the semiconductor device is an integrated device comprised of at least a transistor device and a light emitting device, or at least a light emitting device and a power diode device, or at least a transistor device and a power diode device, or multiple light emitting devices, or multiple transistor devices, or multiple power diode devices, or any combination thereof.