Atomic layer deposition of selected molecular clusters

• US 10,002,938 B2
• Filed: 08/20/2014
• Issued: 06/19/2018
• Est. Priority Date: 08/20/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US14/464,604
• Publication Number:
  US 20150053930A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257 29
• CPC Class Codes: C23C 14/048 using irradiation by energy or particles
• CPC Class Codes: C23C 14/221 Ion beam deposition C23C14/46, C23C14/48 take precedence
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/285 from a gas or vapour, e.g. condensation
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

Claims

1. A transistor formed on a substrate, the transistor comprising:

a source region;

a drain region;

a channel region extending between the source region and the drain region;

a metal gate region including a metal gate that includes a conductive metal portion;

contacts that couple the source region, the drain region, and the metal gate to a multi-layer metal interconnect structure; and

a molecular cluster thin film contacting the conductive metal portion of the metal gate, the molecular cluster thin film comprising nanoscale molecular clusters including at least two bonded atoms that are different, the nanoscale molecular clusters having a selected atomic structure that determines an electrical characteristic of the transistor, the molecular cluster thin film being between the conductive metal portion of the metal gate and the channel region.

2. The transistor of claim 1 wherein the molecular cluster thin film includes one or more of monomers, dimers, trimers, and tetramers.

3. The transistor of claim 1 wherein the molecular cluster thin film is a work function metal film within the metal gate region, and the electrical characteristic is a threshold voltage at which the transistor is activated.

4. The transistor of claim 1 wherein the contacts comprise metal-insulator-semiconductor contacts to the source region and the drain region, the metal-insulator-semiconductor contacts including the molecular cluster thin film, and wherein the electrical characteristic is contact resistance.

5. The transistor of claim 1 wherein the molecular cluster thin film includes one or more of silver bromide (Ag_xBr_y), lanthanum oxide (La_x O_y) and titanium oxide (Ti_xO_y).

6. The transistor of claim 1 wherein the nanoscale molecular clusters have a size of less than 0.5 nm.

7. The transistor of claim 1 wherein the metal gate and the contacts are recessed below a surface of the substrate.

8. The transistor of claim 1 wherein the molecular cluster thin film is an ionic molecular thin film, and wherein the nanoscale molecular clusters are ionic nanoscale molecular clusters.

9. The transistor of claim 8, further comprising a neutral molecular cluster thin film in the source region and the drain region, wherein the neutral molecular thin film comprises neutral nanoscale molecular clusters.

10. The transistor of claim 9 wherein the neutral nanoscale molecular clusters have a selected spatial orientation.

11. The transistor of claim 8 wherein the ionic nanoscale molecular clusters are positively charged.

12. The transistor of claim 8 wherein the ionic nanoscale molecular clusters have a selected spatial orientation.

13. An n-type semiconductor device, comprising:

a silicon substrate having an oxide layer buried therein;

a negatively-doped source region;

a negatively-doped drain region;

a channel through which current flows between the negatively-doped source region and the negatively-doped drain region;

a neutral molecular cluster thin film in the negatively-doped source region and the negatively-doped drain region, the neutral molecular cluster thin film comprising neutral molecular clusters;

a metal gate region comprising a metal gate capacitively coupled to the channel so as to control the current, the metal gate including a conductive metal portion;

an ionic molecular cluster thin film contacting the conductive metal portion of the metal gate, the ionic molecular cluster thin film comprising ionic molecular clusters, the molecular cluster thin film being between the conductive metal portion of the metal gate and the channel; and

metal-insulator-semiconductor contacts to the source region and the drain region.

14. The n-type semiconductor device of claim 13 wherein the neutral molecular clusters have a selected spatial orientation.

15. The n-type semiconductor device of claim 13 wherein the ionic molecular clusters impart a tensile stress at a silicon/germanium interface in the channel.

16. A p-type semiconductor device, comprising:

a silicon substrate having an oxide layer buried therein;

a positively-doped source region;

a positively-doped drain region;

a channel through which current flows between the positively-doped source region and the positively-doped drain region, the channel having a strained silicon interface;

a metal gate region comprising a metal gate capacitively coupled to the channel so as to control the current, the metal gate including a conductive metal portion and a dielectric portion;

a molecular cluster thin film contacting the conductive metal portion of the metal gate region, the molecular cluster thin film being between the conductive metal portion and the dielectric portion of the first metal gate structure, the molecular cluster thin film comprising ionic clusters; and

contacts to the positively-doped source region and the positively-doped drain region.

17. The p-type semiconductor device of claim 16 wherein the ionic clusters have a selected spatial orientation.

18. The p-type semiconductor device of claim 16 wherein the ionic clusters impart a compressive stress at the strained silicon interface in the channel.

19. A device, comprising:

a metal thin film, including a plurality of ionic clusters having a selected spatial orientation;

a semiconductor substrate;

a transistor on the semiconductor substrate, the transistor having a channel and a metal gate above the channel, the metal gate including a conductive metal material, the metal thin film being in contact with the conductive metal material of the metal gate of the transistor, the metal thin film being between the conductive metal material of the metal gate and the channel.

20. The device of claim 19 wherein a surface of the semiconductor substrate is electrically charged.

21. A device, comprising:

a substrate; and

a first transistor on the substrate, the first transistor including;

a first source;

a first drain;

a first metal gate structure that includes a conductive metal portion and a dielectric portion; and

a first molecular cluster thin film in contact with the conductive metal portion of the first metal gate structure, the first molecular cluster thin film being between the conductive metal portion and the dielectric portion of the first metal gate structure.

22. The device of claim 21 wherein the first transistor includes a channel that extends between the first source and first drain, the first metal gate structure being on the channel.

23. The device of claim 22 wherein the first molecular cluster thin film is in contact with a bottom surface and sides surfaces of the conductive metal portion of the first metal gate structure.

24. The device of claim 21, further comprising:

a second transistor on the substrate, the second transistor including;

a second source;

a source contact;

a second drain;

a drain contact;

a second metal gate structure;

a second molecular cluster thin film in contact with the source contact and is between the source contact and the second source; and

a third molecular cluster thin film in contact with the drain contact and is between the drain contact and the second drain.

25. The device of claim 24 wherein the second and third molecular cluster thin film include molecular clusters of the same structure.

26. The device of claim 24 wherein a structure of the first molecular cluster thin film is different from a structure of the second molecular cluster thin film.