Semiconductor device suppressing current leakage in a bootstrap diode

• US 10,002,961 B2
• Filed: 06/06/2014
• Issued: 06/19/2018
• Est. Priority Date: 06/14/2013
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Yamaji, Masaharu
• Primary Examiner(s): CHEN, DAVID Z
• Application Number:
  US14/781,244
• Publication Number:
  US 20160056282A1
• Time in Patent Office: 1,474 Days
• Field of Search: 257139, 257329, 257493, 257495, 257E29255, 257E29262
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7818 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00

Abstract

In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n⁻-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.

Claims

1. A semiconductor device comprising:

a p-type semiconductor substrate;

an n-type buried layer formed on the semiconductor substrate;

an n-type semiconductor layer formed on the buried layer;

a floating potential region provided in a part of the semiconductor layer;

a p-type first separation region surrounding the part of the semiconductor layer where the floating potential region is provided, the first separation region being in contact with the semiconductor substrate, and spaced apart from the floating potential region to be formed in an annular shape;

a first insulating separation region provided beneath the semiconductor layer between the floating potential region and the first separation region;

a diode formed above the first insulating separation region;

a p-type second separation region spaced apart from the first separation region to surround, in an annular shape, a region where the diode is located, and reach beneath the semiconductor layer from a surface of the semiconductor layer;

an n-type source region formed in an upper part of the first separation region;

an n-type drain contact region of a transistor including the source region, the drain contact region being formed in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region; and

a drain drift region of the transistor comprising the n-type buried layer beneath the first insulating separation region.

2. The semiconductor device according to claim 1, wherein the diode includes:

a p-type anode region spaced apart from the second separation region and formed in another upper part of the semiconductor layer above the first insulating separation region; and

the cathode region of n-type spaced apart from the anode region and the floating potential region between the anode region and the floating potential region and formed in the another upper part of the semiconductor layer above the first insulating separation region.

3. The semiconductor device according to claim 2, wherein the transistor further includes a gate electrode formed, via a gate insulating film, above the first separation region located between the source region and the drain contact region.

4. The semiconductor device according to claim 3, wherein a logic circuit is integrated on the floating potential region.

5. The semiconductor device according to claim 4, further comprising

a p-type third separation region that reaches the first insulating separation region from the surface of the semiconductor layer between the cathode region and the drain contact region.

6. The semiconductor device according to claim 5, further comprising

a second insulating separation region provided beneath the semiconductor layer so as to cover an area below the logic circuit and a p-type fourth separation region that reaches the second insulating separation region from the surface of the semiconductor layer between the drain contact region and the floating potential region.

7. The semiconductor device according to claim 5, wherein the third separation region is electrically connected to a low potential-side of a power supply of the logic circuit.

8. The semiconductor device according to claim 6, wherein the fourth separation region is electrically connected to a low potential-side of a power supply of the logic circuit.

9. The semiconductor device according to claim 6, wherein the second separation region, the third separation region, the fourth separation region, the anode region, and the cathode region have closed annular planar shapes.

10. The semiconductor device according to claim 6, wherein the second insulating separation region is a cavity.

11. The semiconductor device according to claim 1, wherein a distance between the drain contact region and another contact region in the floating potential region is longer than a diffusion length of holes that are injected from an anode region of the diode.

12. The semiconductor device according to claim 1, wherein the first insulating separation region is a cavity.

13. The semiconductor device according to claim 1, comprising a conduction path that connects the cathode region and the floating potential region.

14. The semiconductor device according to claim 1, wherein the buried layer comprises a diffusion layer formed in an upper part of the semiconductor substrate, and the semiconductor layer comprises an epitaxial growth layer formed on the buried layer.

15. The semiconductor device according to claim 1, wherein the buried layer comprises a first epitaxial growth layer formed on the semiconductor substrate, and the semiconductor layer comprises a second epitaxial growth layer formed on the first epitaxial growth layer.

16. A semiconductor device comprising:

a p-type semiconductor substrate;

an n-type buried layer formed on the semiconductor substrate;

an n-type semiconductor layer formed on the buried layer;

a floating potential region provided in a part of the semiconductor layer;

a p-type first separation region surrounding the part of the semiconductor layer where the floating potential region is provided, the first separation region being in contact with the semiconductor substrate, and spaced apart from the floating potential region to be formed in an annular shape;

a first insulating separation region provided beneath the semiconductor layer between the floating potential region and the first separation region;

a diode formed above the first insulating separation region;

a p-type second separation region spaced apart from the first separation region to surround, in an annular shape, a region where the diode is located, and reach beneath the semiconductor layer from a surface of the semiconductor layer;

a p-type base region formed in another upper part of the semiconductor layer between the first separation region and the second separation region;

an n-type source region formed on an upper part of the base region;

an n-type drain contact region of a transistor including the base region and the source region, the drain contact region being formed in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region; and

a drain drift region of the transistor comprising the n-type buried layer beneath the first insulating separation region.

17. A semiconductor device comprising:

a p-type semiconductor substrate;

an n-type buried layer formed on the semiconductor substrate;

a floating potential region provided on the buried layer, a logic circuit being formed in the floating potential region;

an n-type semiconductor layer having the same thickness as the floating potential region and located in an island shape on the buried layer so as to surround the floating potential region;

a p-type first separation region provided in an annular shape so as to surround the semiconductor layer and spaced apart from the floating potential region to reach the semiconductor substrate from an upper surface of the semiconductor layer;

a first insulating separation region provided in the buried layer between the floating potential region and the first separation region;

a diode formed above the first insulating separation region;

a p-type second separation region spaced apart from the first separation region, formed in an annular shape so as to surround a part of the semiconductor layer where the diode is located, and passing through the semiconductor layer;

an n-type source region of a transistor, the source region being provided on an upper part of the first separation region;

an n-type drain contact region of the transistor, the drain contact region being provided in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region; and

a drain drift region of the transistor comprising the n-type buried layer beneath the first insulating separation region.

18. The semiconductor device according to claim 17, wherein the diode includes:

a p-type anode region formed in the semiconductor layer above the first insulating separation region; and

the cathode region of n-type formed in the semiconductor layer between the anode region and the floating potential region.

19. The semiconductor device according to claim 17, wherein the transistor uses, as a base region, a part of the upper part of the first separation region located between the source region and the drain contact region, wherein the transistor further includes a gate electrode formed above the base region via a gate insulating film.

20. A semiconductor device comprising:

a p-type semiconductor substrate;

an n-type buried layer formed on the semiconductor substrate;

a floating potential region provided on the buried layer, a logic circuit being formed in the floating potential region;

an n-type semiconductor layer having the same thickness as the floating potential region and located in an island shape on the buried layer so as to surround the floating potential region;

a p-type first separation region provided in an annular shape so as to surround the semiconductor layer and spaced apart from the floating potential region to reach the semiconductor substrate from an upper surface of the semiconductor layer;

a first insulating separation region provided in the buried layer between the floating potential region and the first separation region;

a diode formed above the first insulating separation region;

a p-type second separation region spaced apart from the first separation region, formed in an annular shape so as to surround a part of the semiconductor layer where the diode is located, and passing through the semiconductor layer;

a p-type base region of a transistor, the base region being formed in an upper part of the semiconductor layer between the first separation region and the second separation region;

an n-type source region of the transistor, the source region being formed on an upper part of the base region;

an n-type drain contact region of the transistor, the drain contact region being provided in another upper part of the semiconductor layer between a cathode region of the diode and the floating potential region; and

a drain drift region of the transistor comprising the n-type buried layer beneath the first insulating separation region.