Semiconductor device and manufacturing method thereof

• US 10,002,969 B2
• Filed: 01/17/2017
• Issued: 06/19/2018
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Yeh, Chih Chieh, Wu, Cheng-Hsien
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/407,839
• Publication Number:
  US 20170155001A1
• Time in Patent Office: 518 Days
• Field of Search: None
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Claims

1. A semiconductor device, comprising:

channel layers disposed and vertically arranged over a substrate;

a source/drain region disposed over the substrate;

a gate dielectric layer disposed on and wrapping each of the channel layers;

a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers; and

sidewall spacers disposed on opposing sidewalls of the gate electrode layer, wherein;

each of the channel layers includes a semiconductor wire made of a first semiconductor material,

the semiconductor wire extends into the source/drain region,

the semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material, and

an end portion of the second semiconductor material penetrates into one of the sidewall spacers and is in contact with the channel layers under the one of the sidewall spacers.

2. The semiconductor device of claim 1, wherein the first semiconductor material is Si and the second semiconductor material is at least one of SiP, SiCP and SiC.

3. The semiconductor device of claim 1, wherein the first semiconductor material is Si and the second semiconductor material is at least one of SiGe and Ge.

4. The semiconductor device of claim 1, wherein a thickness of a part of the semiconductor wire wrapped by the gate electrode layer is greater than a thickness of a part of the semiconductor wire wrapped by the second semiconductor material.

5. The semiconductor device of claim 1, further comprising:

an isolation insulating layer disposed over the substrate; and

a fin structure at least partially embedded in the isolation insulating layer,

wherein the channel layers are disposed over the fin structure.

6. The semiconductor device of claim 5, wherein a bottom most channel layer among the channel layer is in contact with the fin structure.

7. The semiconductor device of claim 5, wherein the fin structure is made of a same material as the channel layers.

8. A semiconductor device, comprising:

a channel layer disposed over a substrate;

a source/drain region disposed over the substrate;

a gate dielectric layer disposed on the channel layer; and

a gate electrode layer disposed on the gate dielectric layer, wherein;

the channel layer includes first semiconductor wires made of a first semiconductor material and second semiconductor wires made of a second semiconductor material different from the first semiconductor material, stacked alternately,

the first semiconductor wires extends into the source/drain region, and

the first semiconductor wires in the source/drain regions are wrapped around by a third semiconductor material, respectively.

9. The semiconductor device of claim 8, wherein the first semiconductor material is made of SiGe or Ge.

10. The semiconductor device of claim 9, wherein the second semiconductor material is made of Si or a Si based compound.

11. The semiconductor device of claim 10, wherein the third semiconductor material includes at least one of Si, SiGe, Ge SiP, SiCP and SiC.

12. The semiconductor device of claim 8, wherein in a cross section along direction perpendicular to a source-drain direction, a cross sectional area of the first semiconductor wires is greater than a cross sectional area of the second semiconductor wires.

13. The semiconductor device of claim 8, wherein one second semiconductor wires connect adjacent two first semiconductor wires.

14. The semiconductor device of claim 8, wherein a thickness of a part of the first semiconductor wires at the gate electrode layer is greater than a thickness of a part of the first semiconductor wires at the source/drain region.

15. The semiconductor device of claim 8, further comprising:

an isolation insulating layer disposed over the substrate; and

a fin structure at least partially embedded in the isolation insulating layer,

wherein the channel layer is disposed over the fin structure.

16. The semiconductor device of claim 15, wherein a bottommost wire among the first semiconductor wires is in contact with the fin structure.

17. The semiconductor device of claim 15, wherein the fin structure is made of a different material than the first semiconductor material.

18. The semiconductor device of claim 17, wherein the fin structure is made of a same material as the second semiconductor material.

19. A semiconductor device, comprising:

a first field effect transistor (FET) including;

first channel layers disposed over a substrate;

a first source/drain region disposed over the substrate;

a first gate dielectric layer disposed on and wrapping each of the first channel layers; and

a first gate electrode layer disposed on the first gate dielectric layer and wrapping each of the first channel layers; and

a second FET including;

a second channel layer disposed over the substrate;

a second source/drain region disposed over the substrate;

a second gate dielectric layer disposed on the second channel layer; and

a second gate electrode layer disposed on the second gate dielectric layer, wherein;

each of the first channel layers includes a semiconductor wire made of a first semiconductor material,

the semiconductor wire extends into the first source/drain region,

the semiconductor wire in the first source/drain regions is wrapped around by a second semiconductor material,

the second channel layer includes second semiconductor wires made of a third semiconductor material and third semiconductor wires made of a fourth semiconductor material different from the third semiconductor material, stacked alternately,

the second semiconductor wires extend into the second source/drain region, and

the second semiconductor wires in the source/drain regions are wrapped around by a fifth semiconductor material, respectively.