Methods for forming thermoelectric elements

• US 10,003,004 B2
• Filed: 04/29/2015
• Issued: 06/19/2018
• Est. Priority Date: 10/31/2012
• Status: Expired due to Fees

• Current Assignee: Matrix Industries, Inc.
• Original Assignee: Matrix Industries, Inc.
• Inventors: Boukai, Akram I., Tham, Douglas W.
• Primary Examiner(s): Vu, Vu A
• Application Number:
  US14/700,082
• Publication Number:
  US 20150325772A1
• Time in Patent Office: 1,147 Days
• Field of Search: 438 54
• CPC Class Codes: H01L 21/02019 Chemical etching
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H10N 10/01 Manufacture or treatment
• CPC Class Codes: H10N 10/17 characterised by the structure or configuration of the cell or thermocouple forming the device

Abstract

The present disclosure provides a method for forming a thermoelectric device, comprising providing a semiconductor substrate and providing a first layer of an etching material adjacent to the semiconductor substrate. The etching material facilitates the etching of the semiconductor substrate upon exposure to an oxidizing agent and a chemical etchant. Next, a second layer of a semiconductor oxide is provided adjacent to the first layer, and the second layer is patterned to form a pattern of holes or wires. The second layer and first layer are then sequentially etched to expose portions of the semiconductor substrate. Exposed portions of the semiconductor substrate are then contacted with an oxidizing agent and a chemical etchant to transfer the pattern to the semiconductor substrate.

Claims

1. A method for forming a thermoelectric device, comprising:

(a) providing a semiconductor substrate;

(b) providing a first layer of an etching material adjacent to said semiconductor substrate, wherein said etching material facilitates the etching of said semiconductor substrate upon exposure to an oxidizing agent and a vapor chemical etchant;

(c) providing a second layer of a semiconductor oxide adjacent to said first layer;

(d) patterning said second layer to form a pattern of holes or wires;

(e) sequentially etching said second layer and said first layer to expose portions of said semiconductor substrate; and

(f) contacting exposed portions of said semiconductor substrate to said oxidizing agent and said vapor chemical etchant while applying an electrical potential to said semiconductor substrate, to transfer said pattern to said semiconductor substrate.

2. The method of claim 1, wherein (d) comprises forming a pattern of holes.

3. The method of claim 2, further comprising, between (c) and (d):

providing a third layer of an etch block material adjacent to said second layer; and

patterning said third layer to form said pattern of holes.

4. The method of claim 3, wherein (e) further comprises etching said second and said first layer at a higher rate than said etch block material.

5. The method of claim 1, wherein said electrical potential is a negative potential bias applied across said semiconductor substrate.

6. The method of claim 1, wherein said oxidizing agent is selected from the group consisting of O₂, O₃, NO₂ and H₂O₂, and wherein said vapor chemical etchant is selected from the group consisting of HF, HCl, HBr and HI.

7. The method of claim 1, wherein in (e), said second layer and said first layer are etched by reactive-ion etching.

8. The method of claim 1, wherein (f) further comprises forming holes in or wires from said semiconductor substrate, which holes or wires have aspect ratios from about 100-to-1 to about 100,000,000-to-1.

9. The method of claim 1, wherein in (f) said semiconductor substrate is etched at a rate from about 0.1 nanometers/second to about 10,000 nanometers/second.

10. The method of claim 1, wherein (f) further comprises forming holes in or wires from said semiconductor substrate, which holes or wires have aspect ratios from about 2011:

11-to-1 to about 100,000,000-to-1.

11. The method of claim 1, wherein (f) further comprises forming holes in or wires from said semiconductor substrate, and wherein surfaces of said semiconductor substrate exposed by said holes or wires have a roughness between about 0.5 nanometers (nm) and 50 nm across said holes or wires as measured by transmission electron microscopy.

12. The method of claim 1, wherein said thermoelectric device has a figure-of-merit from about 0.1 to about 2.5.

13. The method of claim 12, wherein said thermoelectric device has a figure-of-merit from about 0.1 to about 0.5.

14. The method of claim 2, wherein said pattern of holes comprises monodisperse holes.

15. The method of claim 3, wherein said etch block material comprises one or more metals.

16. The method of claim 15, wherein said etch block material comprises one or more of chromium, tungsten, molybdenum, tungsten, titanium, or niobium.

17. The method of claim 1, wherein said etching material comprises one or more metals.

18. The method of claim 17, wherein said etching material comprises one or more members selected from the group consisting of gold, silver, platinum, chromium, molybdenum, tungsten, and palladium.