RRAM cell structure with conductive etch-stop layer

• US 10,003,022 B2
• Filed: 03/04/2014
• Issued: 06/19/2018
• Est. Priority Date: 03/04/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi, Tseng, Yuan-Tai, Hsu, Chern-Yow, Liu, Shih-Chang, Tsai, Chia-Shiung
• Primary Examiner(s): Kalam, Abul
• Application Number:
  US14/196,361
• Publication Number:
  US 20150255718A1
• Time in Patent Office: 1,568 Days
• Field of Search: None
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Claims

1. A method of forming a resistive random-access memory (RRAM) device comprising:

providing a semiconductor base surface comprising a metal interconnect structure disposed within a low-k dielectric layer, wherein outer sidewalls of the metal interconnect structure are spaced apart by a first length;

forming a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure;

forming a bottom RRAM electrode layer above the CESL;

forming a variable resistive dielectric layer above the bottom RRAM electrode layer;

forming a top RRAM electrode layer above the variable resistive dielectric layer;

forming a mask over the top RRAM electrode layer, the mask covering some portions of the top RRAM electrode layer while leaving other portions of the top RRAM electrode layer exposed;

performing a first etch to remove the exposed portions of the top RRAM electrode layer and to thereby form a top electrode structure;

forming sidewall spacers about outer sidewalls of the top electrode structure, wherein the sidewall spacers and top electrode structure cover some portions of the variable resistive dielectric layer and leave other portions of the variable resistive dielectric layer exposed; and

performing a second etch with the sidewall spacers and the top electrode structure in place to remove the exposed portions of the variable resistive dielectric layer as well as underlying portions of the bottom RRAM electrode layer, to thereby form a bottom electrode structure and a variable resistive dielectric structure which have outer sidewalls that are aligned, wherein outer sidewalls of the bottom electrode structure are spaced apart by a second length and outer sidewalls of the variable resistive dielectric structure are spaced apart by the second length, the second length being greater than the first length.

2. The method of claim 1, wherein the second etch stops at the CESL such that the bottom electrode structure covers some portions of the CESL while leaving other portions of the CESL exposed;

wherein the second etch is performed such that the formed bottom electrode structure and the variable resistive dielectric structure respectively have their outer sidewalls spaced apart by a first width, and the outer sidewalls of the top electrode structure are spaced apart by a second width which is less than the first width.

3. The method of claim 2, further comprising:

with the bottom electrode structure in place, performing a third etch to remove the exposed portions of the CESL while leaving at least a substantial portion of the covered portions of the CESL in place under the bottom electrode structure.

4. The method of claim 3, wherein, after the third etch, outer sidewalls of the CESL are substantially aligned with the outer sidewalls of the bottom electrode structure.

5. The method of claim 3, wherein the third etch comprises wet etching comprising an alkali base (hydrogen peroxide (H₂O₂) or ammonia-peroxide mixture (APM)) or acid base (hydrogen fluoride (HF) or hydrochloric acid (HCl)) etchants or dry etching comprising chlorine base (Cl₂/BCl₂) or fluorine base (CF₄/CHF₃/CH₂/SF₆) etchants.

6. The method of claim 3, further comprising:

forming a conformal dielectric protection layer that extends continuously along outer sidewalls of the portions of the CESL left in place, along outer sidewalls of the bottom electrode structure, in direct contact with the outer sidewall of the variable resistive dielectric structure, along outer sidewalls of the sidewall spacers, and over an upper surface of the top electrode structure.

7. The method of claim 2, wherein the first and second etches comprise dry etching comprising a chlorine base (Cl₂/BCl₂) or a fluorine base (CF₄/CHF₃/CH₂/SF₆) etchant.

8. The method of claim 2,

wherein the bottom RRAM electrode layer directly contacts the CESL, wherein the bottom RRAM electrode layer comprises a titanium nitride layer over a transitional metal nitride layer;

wherein the variable resistive dielectric layer is a hafnium oxide dielectric layer directly contacting the bottom RRAM electrode layer; and

wherein the top RRAM electrode layer directly contacts the variable resistive dielectric layer, wherein the top RRAM electrode layer comprises a transitional metal nitride layer over a titanium nitride layer.

9. The method of claim 8, further comprising:

with the bottom electrode structure in place, performing a third etch to remove the exposed portions of the CESL while leaving at least a substantial portion of the covered portions of the CESL in place under the bottom electrode structure; and

forming a conformal dielectric protection layer that extends continuously along outer sidewalls of the portions of the CESL left in place, along outer sidewalls of the bottom electrode structure, along outer sidewalls of the sidewall spacers, and over an upper surface of the top electrode structure.

10. A method of forming a resistive random-access memory (RRAM) device comprising:

providing a semiconductor substrate with a metal interconnect structure disposed over the semiconductor substrate, wherein outer sidewalls of the metal interconnect structure are spaced apart by a first length;

forming a conductive etch-stop layer (CESL) over the metal interconnect structure, wherein the CESL directly contacts a metal line and a low-k dielectric which are disposed in an upper conductive layer of the metal interconnect structure;

forming a bottom RRAM electrode layer to directly contact the CESL;

forming a variable resistive dielectric layer to directly contact the bottom RRAM electrode layer;

forming a top RRAM electrode layer to directly contact the variable resistive dielectric layer;

forming a mask over the top RRAM electrode layer, and performing a first etch to remove portions of the top RRAM electrode layer exposed through openings in the mask, and wherein the first etch stops at an uppermost surface of the variable resistive dielectric layer to thereby form a top electrode structure;

forming sidewall spacers about outer sidewalls of the top electrode structure, wherein the sidewall spacers and top electrode structure cover some portions of the variable resistive dielectric layer and leave other portions of the variable resistive dielectric layer exposed; and

with the sidewall spacers and top electrode structure in place and without forming another mask over the top electrode structure, performing a second etch to remove the exposed portions of the variable resistive dielectric layer as well as underlying portions of the bottom electrode, to thereby form a variable resistive dielectric structure and a bottom electrode structure which have outer sidewalls that are aligned, wherein the aligned outer sidewalls of the bottom electrode structure are spaced apart by a second length and outer sidewalls of the variable resistive dielectric structure are spaced apart by the second length, the second length being greater than the first length.

11. The method of claim 10, where the second etch stops at the CESL such that the bottom electrode structure covers some portions of the CESL while leaving other portions of the CESL exposed.

12. The method of claim 10, wherein the CESL is titanium;

titanium nitride;

titanium tungsten;

tungsten;

tungsten nitride;

a combination of titanium, cobalt or tantalum;

or tantalum nitride.

13. The method of claim 12, wherein the dielectric layer is a low-k dielectric layer, the metal line is copper, and the bottom electrode includes a titanium nitride layer over a transitional metal nitride layer.

14. The method of claim 11, further comprising:

with the bottom electrode structure in place, performing a third etch to remove the exposed portions of the CESL while leaving at least a substantial portion of the covered portions of the CESL in place under the bottom electrode structure.

15. The method of claim 14, further comprising:

forming a conformal dielectric protection layer that extends continuously along outer sidewalls of the portions of the CESL left in place, along outer sidewalls of the bottom electrode structure, along outer sidewalls of the sidewall spacers, and over an upper surface of the top electrode structure.

16. The method of claim 10, wherein, after the second etch, outer sidewalls of the bottom electrode structure and the variable resistive dielectric structure are respectively spaced apart by a first width, and outer sidewalls of the top electrode structure are spaced apart by a second width which is less than the first width.

17. The method of claim 14, wherein the second etch comprises dry etching comprising a chlorine base (Cl₂/BCl₂) or a fluorine base (CF₄/CHF₃/CH₂/SF₆) etchant;

and wherein the third etch comprises wet etching comprising an alkali base of hydrogen peroxide (H₂O₂) or ammonia-peroxide mixture or wherein the third etch comprises wet etching comprising an acid base of hydrogen fluoride (HF) or hydrochloric acid (HCl) etchant.

18. A method of forming a resistive random-access memory (RRAM) device comprising:

providing a semiconductor substrate with a metal interconnect structure disposed over the semiconductor substrate, wherein outer sidewalls of the metal interconnect structure are spaced apart by a first length;

forming a conductive etch-stop layer (CESL) over the metal interconnect structure;

forming a bottom RRAM electrode layer, a variable resistive dielectric layer, and a top RRAM electrode layer in that order over the CESL;

performing a first etch to the top RRAM electrode layer to form a top electrode structure;

forming sidewall spacers about outer sidewalls of the top electrode structure; and

performing a second etch to remove exposed portions of the variable resistive dielectric layer and underlying portions of the bottom electrode that are not covered by the top electrode structure and the sidewall spacer, to thereby form a variable resistive dielectric structure and a bottom electrode structure whose outer sidewalls are aligned, wherein the outer sidewalls of the bottom electrode structure are spaced apart by a second length and outer sidewalls of the variable resistive dielectric structure are spaced apart by the second length, the second length being greater than the first length; and

performing a third etch to remove exposed portions of the CESL not covered by the bottom electrode structure, while leaving at least a substantial portion of the CESL covered by the bottom electrode structure in place between the bottom electrode structure and the metal interconnect structure;

wherein the second etch comprises dry etching while the third etch comprises alkali base wet etching.

19. The method of claim 18, wherein the first etch stops at an uppermost surface of the variable resistive dielectric layer.

20. The method of claim 18,

wherein the bottom electrode includes a titanium nitride layer and a transitional nitride layer disposed between the CESL and the titanium nitride layer;

and

wherein the top electrode includes a transitional metal nitride layer disposed over a titanium nitride layer.