Time-based delay line analog comparator

• US 10,003,353 B2
• Filed: 07/18/2017
• Issued: 06/19/2018
• Est. Priority Date: 07/19/2016
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Kris, Bryan, Bartling, Jim, Deutscher, Neil
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US15/652,710
• Publication Number:
  US 20180026648A1
• Time in Patent Office: 336 Days
• Field of Search: 341130-155
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03M 1/1205 Multiplexed conversion systems
• CPC Class Codes: H03M 1/502 using tapped delay lines

Abstract

Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.

Claims

1. A voltage comparator, comprising:

a first input configured to receive a first analog voltage;

a second input configured to receive a second analog voltage;

a first digital delay line configured to propagate a digital input signal through a first delay circuit and the digital input signal through a second delay circuit; and

an output circuit configured to provide a comparator output based upon whether the digital input signal propagated faster through the first or second delay circuit, the comparator output configured to identify whether the first analog voltage or the second analog voltage is greater,

wherein the voltage comparator further includes a voltage to current converter circuit; and

the first digital delay line is further configured to propagate the digital input signal after the first analog voltage is converted to a first current and the second analog voltage is converted to a second current wherein the first current drives the first delay circuit and the second current drives the second delay circuit.

2. The voltage comparator of claim 1, wherein:

the digital input signal represents a logic “

0”

or a logic “

1”

.

3. The voltage comparator of claim 1, wherein:

the output circuit is further configured to provide the comparator output based upon whether the first current or the second current is greater.

4. The voltage comparator of claim 1, wherein:

the output circuit is further configured to identify that the first analog voltage is greater than the second analog voltage based on a determination that the first current is greater than the second current.

5. The voltage comparator of claim 1, wherein:

the output circuit is further configured to identify that the first analog voltage is greater than the second analog voltage based on a logical combination of the values representing the digital input signal propagated through the first delay circuit and the digital input signal propagated through the second delay circuit.

6. The voltage comparator of claim 1 further comprising:

a second digital delay line; and

a multiplexer;

wherein the first and second digital delay lines are configured to alternatively compare analog voltage inputs.

7. The voltage comparator of claim 1, further comprising a thermometer code logic circuit configured to interpret values representing the first analog voltage and the second analog voltage into a comparison identification for the output circuit.

8. The voltage comparator of claim 1, wherein the voltage to current converter is a transconductor configured to convert an input differential voltage between the first analog voltage and the second analog voltage into a differential current representing the first analog voltage and the second analog voltage.

9. The voltage comparator of claim 1, wherein each of the first and second delay circuits includes a chain of current limited buffers.

10. The voltage comparator of claim 1, wherein:

a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;

the comparator further comprises a latch; and

the latch is configured to save data from a slower differential digital delay line upon a completion of a faster differential digital delay line.

11. A microcontroller, comprising:

a plurality of voltage comparators, wherein a first voltage comparator comprises;

a first input configured to receive a first analog voltage;

a second input configured to receive a second analog voltage;

a first digital delay line configured to propagate voltage digital input signal through a first delay circuit and the digital input signal through a second delay circuit; and

an output circuit configured to provide a comparator output based upon whether the digital input signal propagated faster through the first or second delay circuit, the comparator output configured to identify whether the first analog voltage or the second analog voltage is greater,

wherein the voltage comparator further includes a voltage to current converter circuit; and

the first digital delay line is further configured to propagate the digital input signal after the first analog voltage is converted to a first current and the second analog voltage is converted to a second current wherein the first current drives the first delay circuit and the second current drives the second delay circuit.

12. The microcontroller of claim 11, wherein:

the digital input signal represents a logic “

0”

or a logic “

1”

.

13. The microcontroller of claim 11, wherein:

the output circuit is further configured to provide the comparator output based upon whether the first current or the second current is greater.

14. The microcontroller of claim 11, wherein:

the output circuit is further configured to identify that the first analog voltage is greater than the second analog voltage based on a determination that the first current is greater than the second current.

15. The microcontroller of claim 11, wherein:

the output circuit is further configured to identify that the first analog voltage is greater than the second analog voltage based on a logic combination of the values representing the digital input signal propagated through the first delay circuit and the digital input signal propagated through the second delay circuit.

16. The microcontroller of claim 11, wherein the first voltage comparator further comprises:

a second digital delay line; and

a multiplexer;

wherein the first and second digital delay lines are configured to alternatively compare analog voltage inputs.

17. The microcontroller of claim 11, wherein the first voltage comparator further comprises a thermometer code logic circuit configured to interpret values representing the first analog voltage and the second analog voltage into a comparison identification for the output circuit.

18. The microcontroller of claim 11, wherein the voltage to current converter is a transconductor configured to convert an input differential voltage between the first analog voltage and the second analog voltage into a differential current representing the first analog voltage and the second analog voltage.

19. The microcontroller of claim 11, wherein each of the first and second delay circuits includes a chain of current limited buffers.

20. The microcontroller of claim 11, wherein:

a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;

the first voltage comparator further comprises a latch; and

the latch is configured to save data from a slower differential digital delay line upon a completion of a faster differential digital delay line.