Sampler with low input kickback

• US 10,003,454 B2
• Filed: 04/21/2017
• Issued: 06/19/2018
• Est. Priority Date: 04/22/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Ha, Dac
• Application Number:
  US15/494,436
• Publication Number:
  US 20170310455A1
• Time in Patent Office: 424 Days
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.

Claims

1. An apparatus comprising:

a differential current generator configured to receive a signal to be sampled and to responsively generate, at a pair of common nodes, a differential current representative of the received signal;

a sampling interval signal generator configured to receive a symbol clock and to responsively generate a plurality of sampling interval signals on a plurality of sampling interval phase outputs; and

,

a plurality of samplers, each sampler connected to the pair of common nodes, each sampler comprising;

a pre-charging field-effect transistor (FET) pair having a control input connected to one of the plurality of sampling interval phase outputs to pre-charge a pair of output nodes;

a discharging FET pair, each FET of the discharging FET pair connected to a corresponding common node of the pair of common nodes, the discharging FET pair having a control input connected to one of the plurality of sampling interval phase outputs to selectively enable the differential current to discharge the pair of output nodes, forming a differential output voltage; and

a latch connected to the pair of output nodes, the latch configured to latch the differential output voltage.

2. The apparatus of claim 1, wherein the received signal is a differential input signal, and wherein the differential current generator comprises a corresponding current source connected to each common node, each current source receiving a corresponding input signal of the differential input signal.

3. The apparatus of claim 1, wherein the received signal comprises a plurality of signal components representing symbols of a codeword of a vector signaling code.

4. The apparatus of claim 3, wherein the differential current generator comprises a plurality of current sources connected to at least a first node of the pair of common nodes, each current source of the plurality of current sources configured to receive a corresponding signal component of the received signal.

5. The apparatus of claim 4, wherein the plurality of current sources each have an equal current magnitude.

6. The apparatus of claim 4, wherein a first current source of the plurality of current sources has a magnitude larger than a second current source of the plurality of current sources.

7. The apparatus of claim 1, wherein a total magnitude of current sources connected to each common node is balanced.

8. The apparatus of claim 1, wherein the pair of common nodes are virtual ground and configured to isolate the differential current generator from the pair of output nodes.

9. The apparatus of claim 1, further comprising an offset voltage compensation circuit connected to the pair of common nodes configured to inject an offset voltage into the pair of common nodes.

10. The apparatus of claim 1, wherein the sampling interval signals in the plurality of sampling interval signals are non-overlapping.

11. A method comprising:

receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal;

receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase;

pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal;

forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes; and

latching the differential output voltage.

12. The method of claim 11, wherein the received signal to be sampled is a differential input signal.

13. The method of claim 11, wherein the received signal to be sampled comprises a plurality of signal components corresponding to symbols of a codeword of a vector signaling code.

18. The method of claim 11, wherein the pair of common nodes are virtual ground for isolating the received signal to be sampled from the pair of output nodes.

19. The method of claim 11, further comprising injecting an offset voltage into the pair of common nodes.

20. The method of claim 11, wherein the sampling interval signals in the plurality of sampling interval signals are non-overlapping.

14. The method of claim up, wherein generating the differential current comprises forming linear combinations of the signal components of the received signal to be sampled.

15. The method of claim 14, wherein the linear combinations are formed using a plurality of current sources.

16. The method of claim 15, wherein a first current source of the plurality of current sources has a magnitude larger than a second current source of the plurality of current sources.

17. The method of claim 15, wherein the plurality of current sources have equal magnitude.