Techniques for controlling power usage based on network parameters

• US 10,007,317 B2
• Filed: 10/21/2014
• Issued: 06/26/2018
• Est. Priority Date: 04/10/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ehsan, Navid, Appu, Praveen, Challa, Raghu Narayan
• Primary Examiner(s): Patel, Nitin
• Application Number:
  US14/519,855
• Publication Number:
  US 20150293574A1
• Time in Patent Office: 1,344 Days
• Field of Search: 713320
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: H04W 76/28 Discontinuous transmission [DTX]; Discontinuous reception [DRX]
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method for power optimization by an apparatus is disclosed. The method includes identifying one or more network parameters that affect one or more of a processing rate and a power usage of the processor in a connected state. The method also includes identifying a trigger event for the one or more network parameters. The method further includes adjusting a performance of the processor in the connected state when the trigger event occurs.

Claims

1. A method, comprising:

identifying one or more network parameters that affect one or more of a processing rate and a power usage of a processor in a connected state, wherein the one or more network parameters comprise a transfer block size;

identifying a trigger event for the one or more network parameters, wherein the trigger event comprises an average transfer block size being greater than a value; and

adjusting a performance of the processor in the connected state when the trigger event occurs, wherein the adjustment of the performance of the processor causes a power saving mode to be disabled.

2. The method of claim 1, wherein the trigger event for the one or more network parameters is configurable while the processor is in the connected state.

3. The method of claim 1, wherein the trigger event for the one or more network parameters is pre-programmed before the processor is in the connected state.

4. The method of claim 1, wherein the trigger event for the one or more network parameters is an event indicating the processor is ready for a power state change.

5. The method of claim 1, wherein the one or more network parameters further comprise one or more of periodicity of uplink or downlink grants, a number of resource blocks used, modulation and coding scheme information, a signal-to-noise ratio, Doppler information, a transmission mode, a secondary cell status, and a hybrid automatic repeat request (HARQ) status.

6. The method of claim 1, wherein the one or more network parameters further comprise one or more of traffic pattern parameters, channel condition parameters, static configuration parameters, and a transmission mode configuration of a signal.

7. The method of claim 6, wherein the channel condition parameters being monitored comprise a Channel Quality Indicator (CQI) report of a Modulation Coding Scheme (MCS) used in a signal.

8. The method of claim 1, wherein the adjustment of the performance of the processor further comprises causing the processor to enter a power saving mode.

9. The method of claim 8, wherein the adjustment of the performance of the processor further comprises adjusting one or more of a clock rate and a voltage level for specific rails within the processor.

10. The method of claim 1, wherein the adjustment of the performance of the processor further causes the processor to enter a regular power mode.

11. An apparatus, comprising:

a processor;

memory in electronic communication with the processor;

instructions stored in the memory, the instructions being executable to;

identify one or more network parameters that affect one or more of a processing rate and a power usage of a processor in a connected state, wherein the one or more network parameters comprise a transfer block size;

identify a trigger event for the one or more network parameters, wherein the trigger event comprises an average transfer block size being greater than a value; and

adjust a performance of the processor in the connected state when the trigger event occurs, wherein the adjustment of the performance of the processor causes a power saving mode to be disabled.

12. The apparatus of claim 11, wherein the trigger event for the one or more network parameters is configurable while the processor is in the connected state.

13. The apparatus of claim 11, wherein the trigger event for the one or more network parameters is pre-programmed before the processor is in the connected state.

14. The apparatus of claim 11, wherein the trigger event for the one or more network parameters is an event indicating the processor is ready for a power state change.

15. The apparatus of claim 11, wherein the one or more network parameters further comprise one or more of periodicity of uplink or downlink grants, a number of resource blocks used, modulation and coding scheme information, a signal-to-noise ratio, Doppler information, a transmission mode, a secondary cell status, and a hybrid automatic repeat request (HARQ) status.

16. The apparatus of claim 11, wherein the one or more network parameters further comprise one or more of traffic pattern parameters, channel condition parameters, static configuration parameters and a transmission mode configuration of a signal.

17. The apparatus of claim 16, wherein the channel condition parameters being monitored comprise a Channel Quality Indicator (CQI) report of a Modulation Coding Scheme (MCS) used in a signal.

18. The apparatus of claim 11, wherein the adjustment of the performance of the processor further comprises causing the processor to enter a power saving mode.

19. The apparatus of claim 18, wherein the adjustment of the performance of the processor further comprises adjusting one or more of a clock rate and a voltage level for specific rails within the processor.

20. The apparatus of claim of claim 11, wherein the adjustment of the performance of the processor further causes the processor to enter a regular power mode.

21. A non-transitory computer-readable medium having instructions thereon, the instructions comprising:

code for identifying one or more network parameters that affect one or more of a processing rate and a power usage of a processor in a connected state, wherein the one or more network parameters comprise a transfer block size;

code for identifying a trigger event for the one or more network parameters, wherein the trigger event comprises an average transfer block size being greater than a value; and

code for adjusting a performance of the processor in the connected state when the trigger event occurs, wherein the adjustment of the performance of the processor causes a power saving mode to be disabled.

22. The non-transitory computer-readable medium of claim 21, wherein the one or more network parameters further comprise one or more of periodicity of uplink or downlink grants, a number of resource blocks used, modulation and coding scheme information, a signal-to-noise ratio, Doppler information, a transmission mode, a secondary cell status, and a hybrid automatic repeat request (HARQ) status.

23. The non-transitory computer-readable medium of claim 21, wherein the one or more network parameters further comprise one or more of traffic pattern parameters, channel condition parameters, static configuration parameters, and a transmission mode configuration of a signal.

24. The non-transitory computer-readable medium of claim 23, wherein the channel condition parameters being monitored comprise a Channel Quality Indicator (CQI) report of a Modulation Coding Scheme (MCS) used in a signal.

25. The non-transitory computer-readable medium of claim 21, wherein the adjustment of the performance of the processor further comprises causing the processor to enter a power saving mode or a regular power mode.

26. An apparatus, comprising:

means for identifying one or more network parameters that affect one or more of a processing rate and a power usage of a processor in a connected state, wherein the one or more network parameters comprise a transfer block size;

means for identifying a trigger event for the one or more network parameters, wherein the trigger event comprises an average transfer block size being greater than a value; and

means for adjusting a performance of the processor in the connected state when the trigger event occurs, wherein the adjustment of the performance of the processor causes a power saving mode to be disabled.

27. The apparatus of claim 26, wherein the one or more network parameters further comprise one or more of periodicity of uplink or downlink grants, a number of resource blocks used, modulation and coding scheme information, a signal-to-noise ratio, Doppler information, a transmission mode, a secondary cell status, and a hybrid automatic repeat request (HARQ) status.

28. The apparatus of claim 26, wherein the one or more network parameters further comprise one or more of traffic pattern parameters, channel condition parameters, static configuration parameters, and a transmission mode configuration of a signal.

29. The apparatus of claim 28, wherein the channel condition parameters being monitored comprise a Channel Quality Indicator (CQI) report of a Modulation Coding Scheme (MCS) used in a signal.

30. The apparatus of claim 26, wherein the adjustment of the performance of the processor further comprises causing the processor to enter a power saving mode or a regular power mode.