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Non-volatile memory serial core architecture

  • US 10,007,439 B2
  • Filed: 01/06/2017
  • Issued: 06/26/2018
  • Est. Priority Date: 11/27/2006
  • Status: Active Grant
First Claim
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1. A non-volatile memory system comprising:

  • at least one non-volatile memory device; and

    a memory controller communicatively coupled to the least one non-volatile memory device, the memory controller configured to provide to the at least one non-volatile memory device a chip select signal, a clock signal, and at least one common data signal carrying command data, address data and write data,the at least one non-volatile memory device comprising;

    a plurality of non-volatile memory banks,a chip select input configured to receive the chip select signal for enabling the non-volatile memory banks,a clock input configured to receive the clock signal for synchronizing the at least one common data signal, andat least one common data input configured to receive the at least one common data signal for providing the command data, the address data and the write data to the non-volatile memory banks,wherein each non-volatile memory bank comprises;

    a first non-volatile memory sector having non-volatile memory cells coupled to first bitlines and first wordlines, the first bitlines being arranged as m segments where m is an integer value greater than 0,a second non-volatile memory sector having non-volatile memory cells coupled to second bitlines and second wordlines, the second bitlines being arranged as m segments, anda page buffer disposed between the first non-volatile memory sector and the second non-volatile memory sector for selectively coupling one of the first bitlines and the second bitlines of each of the m segments to a predetermined number of data lines, the predetermined number of data lines containing at least a portion of the write data, the page buffer includinga first self-decoding page buffer stage for sensing data from a first bitline, and for providing sensed data corresponding to the first bitline on a corresponding data line in response to an active column select bit latched in a clock signal state, the first self-decoding page buffer stage including an output terminal for providing the active column select bit; and

    a second self-decoding page buffer stage having an input terminal for receiving the active column select bit from the output terminal of the first self-decoding page buffer stage, for sensing data from a second bitline, and providing sensed data corresponding to the second bitline on the corresponding data line in response to the active column select bit latched in a subsequent clock signal state.

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