Computing platform interface with memory management

• US 10,007,528 B2
• Filed: 11/21/2012
• Issued: 06/26/2018
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Therien, Guy M., Diefenbaugh, Paul, Aggarwal, Anil, Henroid, Andrew D., Shrall, Jeremy J., Rotem, Efraim, Sistla, Krishnakanth V., Weissmann, Eliezer, Kumar, Mohan, Jayakumar, Sarathy, Vargas, Jose Andy, Chandwani, Neelam, Rothman, Michael A., Gough, Robert, Doran, Mark
• Primary Examiner(s): Vu, Bai D.
• Application Number:
  US13/683,748
• Publication Number:
  US 20130151569A1
• Time in Patent Office: 2,043 Days
• Field of Search: 707802, 707803, 707804
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 11/3672 Test management
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 16/2282 Tablespace storage structures; Management thereof
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/22 : Microcontrol or microprogram arrangements
• CPC Class Codes: G06F 9/30098 : Register arrangements
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/44 : Arrangements for executing specific programs
• CPC Class Codes: G06F 9/4401 : Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 : Processor initialisation
• CPC Class Codes: G06F 9/4418 : Suspend and resume; Hibernate and awake
• CPC Class Codes: G06F 9/445 : Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Claims

1. An apparatus for memory power management to save power, the apparatus comprising:

one or more memories; and

a firmware including Advanced Configuration and Power Interface (ACPI) components to build, at the time of boot, a memory power state table (MPST) structure, wherein the MPST structure is associated with the one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,

wherein the MPST table structure is stored in a dedicated firmware memory space,

wherein firmware is to use the information in the MPST table to allow the apparatus to save power,

wherein data in the MPST structure is updated by a platform, and

wherein the firmware to update some parts of the MPST structure while the platform is operating.

2. The apparatus of claim 1, wherein the MPST structure includes a table with power state values.

3. The apparatus of claim 1, wherein the MPST structure includes a table with memory power node structure definitions for the one or more memories.

4. The apparatus of claim 1, wherein the MPST structure includes a table with memory power state structure definitions.

5. The apparatus of claim 1, wherein the MPST structure includes a common memory aggregator device structure.

6. The apparatus of claim 1, wherein the one or more memories and the firmware are part of a computer platform that is one of a:

smart-phone,

tablet, or

server computer.

7. The apparatus of claim 1, wherein the memory power nodes represent logical memory regions, associated with the one or more memories, that can be transitioned in and out of memory power states.

8. The apparatus of claim 1, wherein each of the memory power nodes is uniquely identified.

9. The apparatus of claim 1, wherein the memory power state characteristics describe memory power state transitions.

10. The apparatus of claim 1, wherein the firmware to create the MPST structure in a dedicated firmware memory space.

11. A method for memory power management to save power, the method comprising:

building, at the time of boot, a memory power state table (MPST) structure compatible with an Advanced Configuration and Power Interface (ACPI), wherein the MPST structure is associated with one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,

wherein the MPST table structure is stored in a dedicated firmware memory space,

wherein the information in the MPST table is used to allow an apparatus to save power,

wherein data in the MPST structure is updated by a platform, and

wherein the firmware is to update some parts of the MPST structure while the platform is operating.

12. The method of claim 11, wherein the MPST structure includes a table with power state values.

13. The method of claim 11, wherein the MPST structure includes a table with memory power node structure definitions for the one or more memories.

14. The method of claim 11, wherein the MPST structure includes a table with memory power state structure definitions.

15. The method of claim 11, wherein the MPST structure includes a common memory aggregator device structure.

16. The method of claim 11, wherein the memory power nodes represent logical memory regions, associated with the one or more memories, that can be transitioned in and out of memory power states.

17. The method of claim 11, wherein each of the memory power nodes is uniquely identified.

18. The method of claim 11, wherein the memory power state characteristics describe memory power state transitions.

19. A non-transitory computer executable storage media having instructions stored thereon that when executed cause a one or more processors to perform one or more operation for memory power management to save power, the method comprising:

building, at the time of boot, a memory power state table (MPST) structure compatible with an Advanced Configuration and Power Interface (ACPI), wherein the MPST structure is associated with one or more memories, wherein the MPST structure includes a table having information about platform control channel (PCC) information,

wherein the MPST table structure is stored in a dedicated firmware memory space,

wherein the information in the MPST table is used to allow an apparatus to save power,

wherein data in the MPST structure is updated by a platform, and

wherein the firmware is to update some parts of the MPST structure while the platform is operating.