Memory backup management in computing systems

• US 10,007,579 B2
• Filed: 03/11/2016
• Issued: 06/26/2018
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Shaw, Mark A., Lee, Scott Chao-Chueh, Govindan, Sriram, Kelly, Bryan
• Primary Examiner(s): Butler, Sarai E
• Application Number:
  US15/067,644
• Publication Number:
  US 20170262344A1
• Time in Patent Office: 837 Days
• Field of Search: 714 621
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1464 for networked environments
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2201/84 Using snapshots, i.e. a logical point-in-time copy of the data
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: H02J 1/106 for load balancing, symmetrisation, or sharing

Abstract

Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.

Claims

1. A method of managing memory backup in a computing device having a baseboard management controller, main processor, and a memory controller operatively coupled to a hybrid memory device by a data bus, the hybrid memory device having a volatile memory module, a non-volatile memory module, and a module controller operatively coupled to the volatile memory module and the non-volatile memory module, the method comprising:

monitoring, with the baseboard management controller, for a system error in the computing device; and

in response to a system error being detected, with the baseboard management controller,

operating a switch that is in the data bus intermediate between the memory controller and the hybrid memory device and between the baseboard management controller and the hybrid memory device to disengage the memory controller from communicating with and controlling the hybrid memory device and simultaneously engage the baseboard management controller for communicating with and controlling the hybrid memory device; and

subsequent to the memory controller being disengaged from communicating with and controlling the hybrid memory device, with the baseboard management controller, causing the module controller of the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module and persistently store in the non-volatile memory module of the hybrid memory device the copied data from the volatile memory module, without operating the main processor or the memory controller.

2. The method of claim 1, further comprising subsequent to disengaging the memory controller, causing the hybrid memory device to enter into a self-refresh mode in which the hybrid memory device receives power from an auxiliary power source operatively coupled to the hybrid memory device, the auxiliary power source being separated from a main power supply of the computing device.

3. The method of claim 1, further comprising:

subsequent to disengaging the memory controller, causing the hybrid memory device to enter into a self-refresh mode in which the hybrid memory device receives power from an auxiliary power source operatively coupled to the hybrid memory device and separated from a main power supply of the computing device; and

wherein causing the hybrid memory device to copy data includes causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module after the hybrid memory device is in the self-refresh mode.

4. The method of claim 1 wherein:

causing the hybrid memory device to copy data includes transmitting, from the baseboard management controller, a command to the module controller of the hybrid memory device via the data bus, the command causing the module controller to copy data from the volatile memory module to the non-volatile memory module.

5. The method of claim 1 wherein:

causing the hybrid memory device to copy data includes providing a voltage or current signal to a pin of the hybrid memory device, the voltage or current signal causing the module controller to copy data from the volatile memory module to the non-volatile memory module.

6. The method of claim 1, further comprising:

determining whether copying of the data from the volatile memory module to the non-volatile memory module is completed; and

in response to determining that copying of the data from the volatile memory module to the non-volatile memory module is not completed, maintaining the auxiliary power source active and refreshing the volatile memory module with power from the auxiliary power source.

7. The method of claim 1, further comprising:

determining whether copying of the data from the volatile memory module to the non-volatile memory module is completed; and

in response to determining that copying of the data from the volatile memory module to the non-volatile memory module is completed successfully, performing at least one of the following;

allowing the auxiliary power source to be turned off;

or

allowing the computing device to reset.

8. The method of claim 1 wherein:

the method further includes;

determining whether copying of the data from the volatile memory module to the non-volatile memory module is completed successfully; and

in response to determining that copying of the data from the volatile memory module to the non-volatile memory module is completed successfully, resetting the switch to reengage the memory controller with the hybrid memory device and subsequently allowing the computing device to reset.

9. A computing device, comprising:

a main processor operatively coupled to a memory controller with a buffer for holding data to be stored;

a hybrid memory device having a volatile memory module and a non-volatile memory module operatively coupled to one another;

a data bus between the memory controller and the volatile memory module of the hybrid memory device, wherein the memory controller is configured to write data held in the buffer into the volatile memory module of the hybrid memory device via the data bus;

wherein the data bus includes a switch intermediate between the memory controller and the volatile memory module of the hybrid memory device, the switch being configured to controllably disengage the memory controller from the hybrid memory device; and

a baseboard management controller (“

BMC”

) having a digital output to the switch, wherein the BMC is configured to provide a signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device and simultaneously engage the BMC with the hybrid memory device.

10. The computing device of claim 9, wherein the BMC is configured to:

detect a system error related to the main processor or the memory controller; and

provide the signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device and engage the BMC with the hybrid memory device in response to a detected system error.

11. The computing device of claim 9, wherein the BMC is configured to:

detect a system error related to the main processor or the memory controller;

in response to a detected system error,

provide the signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device and engage the BMC with the hybrid memory device via the data bus; and

transmit a command to the hybrid memory device via the data bus, the command causes the hybrid memory device to copy data in the volatile memory module to the non-volatile memory module.

12. The computing device of claim 9, wherein the BMC is configured to:

detect a system error related to the main processor or the memory controller;

in response to a detected system error,

provide the signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device; and

provide a signal to an input pin of the hybrid memory device, the signal to the input pin causes the hybrid memory device to copy data in the volatile memory module to the non-volatile memory module.

13. The computing device of claim 9, wherein the BMC is configured to:

detect a system error related to the main processor or the memory controller;

in response to a detected system error,

provide the signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device;

subsequent to the memory controller being disengaged from the hybrid memory device, cause the hybrid memory device to copy data in the volatile memory module to the non-volatile memory module;

monitor a status of copying the data in the volatile memory module to the non-volatile memory module; and

in response to that copying the data in the volatile memory module to the non-volatile memory module is completed successfully, allow the computing device to reset.

14. The computing device of claim 9, wherein the BMC is configured to:

detect a system error related to the main processor or the memory controller;

in response to a detected system error,

provide the first signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device;

subsequent to the memory controller being disengaged from the hybrid memory device, cause the hybrid memory device to copy data in the volatile memory module to the non-volatile memory module;

monitor a status of copying the data in the volatile memory module to the non-volatile memory module; and

in response to that copying the data in the volatile memory module to the non-volatile memory module is completed successfully, provide a second signal at the digital output to cause the switch to reengage the memory controller to the hybrid memory device.

15. A computer assembly, comprising:

a motherboard carrying;

a memory controller with a buffer for holding data;

a socket configured to receive a hybrid memory device having the volatile memory module and a non-volatile memory module operatively coupled to the volatile memory module;

a data bus between the memory controller and the socket, wherein the memory controller is configured to write data in the buffer into the volatile memory module of the hybrid memory device via the data bus in response to an instruction from the main processor;

a switch in the data bus and intermediate between the memory controller and the socket configured to receive the hybrid memory device, the switch being configured to controllably disengage the memory controller from the hybrid memory device when received in the socket; and

a baseboard management controller (“

BMC”

) having a digital output to the switch, wherein the BMC is configured to provide a signal at the digital output to cause the switch to disengage the memory controller from the hybrid memory device and engage the BMC with the hybrid memory device, wherein the switch is configured to controllably engage the BMC with the hybrid memory device.