Safety features for high level design

• US 10,007,748 B2
• Filed: 06/26/2017
• Issued: 06/26/2018
• Est. Priority Date: 11/02/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Titley, Adam
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/633,461
• Publication Number:
  US 20170293703A1
• Time in Patent Office: 365 Days
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Claims

1. A tangible, non-transitory, and computer-readable media storing instructions that, when executed by one or more processors, cause one or more processors to:

identify at least one programming language construct associated with a safety data type of an algorithmic description representation of a circuit design, wherein the algorithmic description representation is specified in a first language;

and

generate a second representation of the circuit design based on the algorithmic description representation and the safety data type, the second representation is specified in a second language and includes at least one safety feature that is based at least in part on the safety data type, wherein the second representation is used to configure a manufactured programmable logic device after manufacturing of the programmable logic device has been completed.

2. The tangible, non-transitory, and computer-readable media of claim 1, wherein the algorithmic description representation is a control-flow-based representation.

3. The tangible, non-transitory, and computer-readable media of claim 2, wherein the first language is compatible with a standardized framework for programs that execute across multiple heterogeneous platforms.

4. The tangible, non-transitory, and computer-readable media of claim 1, wherein the first language comprises a high-level synthesis programming language.

5. The tangible, non-transitory, and computer-readable media of claim 1, wherein the second representation of the circuit design is a data-flow-based representation.

6. The tangible, non-transitory, and computer-readable media of claim 1, wherein the safety data type comprises a safety-critical function.

7. The tangible, non-transitory, and computer-readable media of claim 6, wherein the safety-critical function comprises a safe version of a standard function.

8. The tangible, non-transitory, and computer-readable media of claim 1, wherein the at least one programming language construct includes at least one function having a return type defined using the safety data type.

9. The tangible, non-transitory, and computer-readable media of claim 1, wherein the at least one programming language construct includes at least one function including at least one parameter defined using the safety data type.

10. The tangible, non-transitory, and computer-readable media of claim 1, wherein the second representation is a data-flow-based representation.

11. The tangible, non-transitory, and computer-readable media of claim 10, wherein the second representation comprises a register transfer language.

12. The tangible, non-transitory, and computer-readable media of claim 10, wherein the second language comprises a hardware description language.

13. A system comprising:

one or more memory devices storing non-transitory processor-executable code configured to implement instructions;

one or more processors to execute the processor-executable code to cause the one or more processors to;

identify at least one programming language construct associated with a safety data type of an algorithmic description representation of a circuit design, wherein the algorithmic description representation is specified in a first language;

generate a second representation of the circuit design based on the algorithmic description representation and the safety data type, wherein the second representation being provided in a second language and including at least one safety feature that is based at least in part on the safety data type; and

configuring a programmable logic device after the programmable logic device has been manufactured.

14. The system of claim 13, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

15. The system of claim 13, wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the safety data type.

16. The system of claim 15, wherein the instructions are configured to cause the one or more processors to perform a compiling including the identifying and the generating, wherein the compiling includes:

identifying the one or more directives;

identifying the one or more header files;

accessing the one or more header files;

retrieving the contents of the one or more header files; and

including the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

17. The system of claim 13, wherein the at least one programming language construct includes at least one variable defined using the safety data type.

18. The system of claim 13, wherein the at least one programming language construct includes at least one function having a return type defined using the safety data type.

19. The system of claim 13, wherein the at least one programming language construct includes at least one function including at least one parameter defined using the safety data type.

20. A method comprising:

identifying at least one programming language construct associated with a safety data type of an algorithmic description representation of a circuit design, wherein the algorithmic description representation is specified in a first language;

generating a second representation of the circuit design based on the algorithmic description representation and the safety data type, wherein the second representation is specified in a second language and includes at least one safety feature that is based at least in part on the safety data type; and

configuring a programmable logic device after the programmable logic device has been manufactured.

21. The method of claim 20, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.