Converged adaptive compensation scheme

• US 10,007,749 B2
• Filed: 09/23/2014
• Issued: 06/26/2018
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Roger K., Rusu, Stefan, Martin, Aaron
• Primary Examiner(s): Chung, Hoon J
• Application Number:
  US14/494,190
• Publication Number:
  US 20160087918A1
• Time in Patent Office: 1,372 Days
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence

Abstract

Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.

Claims

1. A packaged processor chip comprising:

logic to convert output of at least one sensor to a digital sensing signal;

a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data, wherein the circuit data is configured as packets of data, and wherein at least one packet of data includes a type field to indicate a type of circuit endpoint; and

one or more communication interfaces, coupled to the router, to forward the circuit data to the circuit endpoint, wherein the logic, router and one or more communication interfaces are within the packaged processor chip; and

wherein at least one of the packets of data includes a data field to provide a code for the circuit endpoint; and

wherein the circuit endpoint includes one or more circuits which are to be compensated for a parameter, according to the packets of data.

2. The packaged processor chip of claim 1, wherein the at least one sensor is one of:

voltage sensor;

temperature sensor;

or

process sensor.

3. The packaged processor chip of claim 1, wherein the logic comprises an analog to digital converter to convert the output of the at least one sensor to the digital sensing signal.

4. The packaged processor chip of claim 1, wherein the at least one sensor is positioned in one of a multiple of dies in a three dimensional integrated circuit.

5. The packaged processor chip of claim 1, wherein the router includes:

an encoder to encode the digital sensing signal to generate the circuit data as the packets of data.

6. The packaged processor chip of claim 1, wherein the code is a compensation code for the circuit endpoint.

7. The packaged processor chip of claim 5 comprises firmware to program the encoder.

8. The packaged processor chip of claim 5, wherein the router is to periodically transmit the packets of data over the one or more communication interfaces to the circuit endpoint.

9. The packaged processor chip of claim 5, wherein the router is to transmit the packets of data over the one or more communication interfaces to the circuit endpoint according to the type of the circuit endpoint.

10. The packaged processor chip of claim 5, wherein the circuit endpoint includes a decoder to decode the packets of data.

11. The packaged processor chip of claim 1, wherein the at least one sensor is either positioned on-die or off-die.

12. The packaged processor chip of claim 1, wherein the circuit endpoint is operable to be to trimmed in real time using data from the sensor.

13. The packaged processor chip of claim 1, wherein the sensor comprises a process measuring structure.

14. The packaged processor chip of claim 13, wherein the process measuring structure comprises a ring oscillator.

15. The packaged processor chip of claim 1, wherein the one or more communication interfaces comply with at least one of:

IOSF protocol, AMBA protocol, or CoreConnect protocol.

16. A method comprising:

providing one or more digital sensing signals from a plurality of sensors;

receiving the one or more digital sensing signals;

generating packets of data using the one or more digital sensing signals; and

providing the packets of data to one or more destinations; and

compensating a circuit in the one or more destinations for a parameter according to the packets of data.

17. The method of claim 16, wherein the plurality of sensors includes at least one of:

voltage sensors;

temperature sensors;

or

process sensors.

18. The method of claim 16 comprises converting output of at least one sensor, of the plurality of sensors, to a digital sensing signal.

19. The method of claim 16 comprises positioning the plurality of sensors at various locations of one or more dies in a three dimensional or a two dimensional integrated circuit.

20. The method of claim 16 comprises encoding the one or more digital sensing signals to generate packets of data.

21. The method of claim 20 comprises programming the encoding operation of one or more routing logics.

22. The method of claim 16 comprises periodically transmitting the packets of data to the one or more destinations.

23. The method of claim 16 comprises transmitting the packets of data to the one or more destinations according to types of the one or more destinations.

24. The method of claim 16 comprises decoding the packets of data at the one or more destinations.

25. The method of claim 16, wherein the plurality of sensors includes on-die and off-die sensors or circuits.

26. A system comprising:

a memory;

a processor coupled to the memory, the processor including;

logic to convert output of at least one sensor to a digital sensing signal;

a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data, wherein the circuit data is configured as packets of data, wherein at least one packet of data includes a type field to indicate a type of a circuit endpoint; and

one or more communication interfaces, coupled to the router, to forward circuit data to the circuit endpoint, wherein the processor and memory are within a packaged processor chip, and wherein at least one of the packets of data includes a data field to provide a code for the circuit endpoint, wherein the code is a compensation code for the circuit endpoint; and

a wireless interface to allow the processor to couple to another device.

27. The system of claim 26 further comprises a display interface to allow a display unit to display content processed by the processor.