Forming a protective layer to prevent formation of leakage paths

• US 10,008,416 B2
• Filed: 11/30/2016
• Issued: 06/26/2018
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Leo, Lin, Louis
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US15/364,488
• Publication Number:
  US 20180151445A1
• Time in Patent Office: 573 Days
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Claims

1. A method of fabricating a semiconductor device, comprising:

receiving a semiconductor device that includes a first interlayer dielectric (ILD) and a second ILD disposed over the first ILD, wherein a first via is disposed in the first ILD, and wherein spacers are disposed on sidewalls of the first via, the spacers comprising a first dielectric material;

forming a via hole in the second ILD, the via hole exposing the first via;

forming a protective layer in the via hole; and

performing an etching process after the forming of the protective layer, wherein the etching process is configured to etch away the first dielectric material.

2. The method of claim 1, further comprising:

before the etching process, removing a bottom segment of the protective layer.

3. The method of claim 2, wherein:

before the forming of the protective layer, a first portion of the spacers is exposed by the via hole; and

after the removing of the bottom segment, a remaining portion of the protective layer still covers up the first portion of the spacers.

4. The method of claim 3, wherein the remaining portion of the protective layer protects the first portion of the spacers from being etched in the etching process.

5. The method of claim 1, wherein the forming of the protective layer comprises forming the protective layer that comprises a material different from the first dielectric material.

6. The method of claim 5, wherein the material of the protective layer has an etching selectivity with the first dielectric material during the etching process.

7. The method of claim 5, wherein:

the first dielectric material comprises silicon nitride; and

the material of the protective layer comprises a polymer.

8. The method of claim 1, wherein the spacers have a first material composition, and the first ILD or the second ILD has a second material composition different from the first material composition.

9. The method of claim 1, wherein:

the semiconductor device further comprises a gate disposed below the first ILD;

the gate includes a gate electrode and a hard mask disposed over the gate electrode; and

the etching process removes a portion of the hard mask to expose the gate electrode.

10. The method of claim 9, wherein the hard mask and the spacers have the same material composition.

11. The method of claim 1, further comprising:

forming a second conductive via in the via hole.

12. The method of claim 11, further comprising:

before the forming of the second conductive via, removing the protective layer.

20. The method of claim 1, wherein the forming of the protective layer comprises forming methane, methylene, or a methylene bridge as the protective layer.

13. A method of fabricating a semiconductor device, comprising:

forming a gate structure over a substrate, the gate structure including a gate electrode and a hard mask located over the gate electrode, wherein the hard mask comprises a first dielectric material;

forming a first interlayer dielectric (ILD) over the gate structure, wherein the first ILD comprises a second dielectric material different from the first dielectric material;

forming a first via in the first ILD, wherein sidewalls of the first via are surrounded by spacers, the spacers comprising the first dielectric material;

forming a second ILD over the first ILD;

forming a via hole in the second ILD, the via hole exposing the first via;

forming a protective layer in the via hole;

removing a bottom segment of the protective layer; and

thereafter performing an etching process, wherein a remaining segment of the protective layer prevents an etching of the spacers during the etching process.

14. The method of claim 13, wherein:

the etching process is configured to etch away the first dielectric material; and

the protective layer comprises a material having an etching selectivity with the first dielectric material during the etching process.

15. The method of claim 14, wherein:

the first dielectric material comprises silicon nitride; and

the material of the protective layer comprises a polymer.

16. The method of claim 13, wherein the etching process is configured to etch away a portion of the hard mask to expose the gate electrode.

17. The method of claim 13, further comprising:

after the etching process, removing the protective layer; and

forming a second conductive via in the via hole after the protective layer has been removed.

18. A method of fabricating a semiconductor device, comprising:

forming a gate structure over a substrate, the gate structure including a gate electrode and a hard mask located over the gate electrode, wherein the hard mask comprises silicon nitride;

forming a first interlayer dielectric (ILD) over the gate structure, wherein the first ILD comprises silicon oxide;

forming a first via in the first ILD, wherein sidewalls of the first via are surrounded by spacers that comprise silicon nitride;

forming a second ILD over the first ILD, wherein the second ILD comprises silicon nitride;

forming a via hole in the second ILD, wherein the via hole exposes the via and exposes a first portion of the spacers;

forming a protective layer in the via hole, wherein the protective layer comprises a polymer;

removing a bottom segment of the protective layer, wherein a remaining segment of the protective layer still covers the first portion of the spacers; and

performing an etching process to remove a portion of the hard mask so that a portion of the gate electrode becomes exposed, wherein the polymer has an etching selectivity with the silicon nitride such that the remaining segment of the protective layer prevents the spacers from being inadvertently etched during the etching process.

19. The method of claim 18, further comprising:

after the etching process, removing the protective layer; and

thereafter forming a second conductive via in the via hole.