Microelectronic element with bond elements to encapsulation surface

• US 10,008,477 B2
• Filed: 10/05/2016
• Issued: 06/26/2018
• Est. Priority Date: 09/16/2013
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Haba, Belgacem, Crisp, Richard Dewitt, Zohni, Wael
• Primary Examiner(s): MAZUMDER, DIDARUL A
• Application Number:
  US15/286,086
• Publication Number:
  US 20170025390A1
• Time in Patent Office: 629 Days
• Field of Search: 257784, 438617
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/1191 Forming a passivation layer after forming the bump connector
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13076 : being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1369 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16105 : the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16108 : the bump connector not being orthogonal to the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73103 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/742 : Apparatus for manufacturing bump connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92142 : the first connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92143 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49 : wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/742 : Apparatus for manufacturing bump connectors
• CPC Class Codes: H01L 24/745 : Apparatus for manufacturing wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Claims

1. A microelectronic structure, comprising:

a first semiconductor die having a first surface, the first surface having a first region and a second region, a plurality of first electrically conductive elements at the first surface of the first semiconductor die;

a second semiconductor die mounted on the first semiconductor die within the first region the second semiconductor die has a front surface and a plurality of second electrically conductive elements at the front surface, wherein the front surface of the second semiconductor die faces away from the first surface of the first semiconductor die;

first wire bonds having bases joined to respective ones of the first conductive elements, the first wire bonds further having end surfaces remote from the bases, the first wire bonds defining edge surfaces extending between the bases and the end surfaces thereof; and

a compliant material layer overlying the first surface of the first semiconductor die and overlying the second semiconductor die, the compliant material layer contacting edge surfaces of first portions of the first wire bonds and fully encapsulating each first portion such that the first portions of the first wire bonds are separated from one another by the compliant material layer, the compliant material layer further having a surface facing away from the first surface of the first semiconductor die, wherein second portions of the first wire bonds including the end surfaces are disposed above the surface of the compliant material layer, the second portions configured to connect with contacts of a substrate external to the microelectronic structure,

the microelectronic structure further comprising a plurality of second wire bonds having bases joined to the second electrically conductive elements and having free ends remote from the bases of the second wire bonds, the free ends of the second wire bonds remote from the first surface of the second semiconductor die, and the free ends of the second wire bonds including end surfaces of the second wire bonds, the second wire bonds defining edge surfaces extending between the bases of the second wire bonds and the end surfaces of the second wire bonds,

wherein the compliant material layer overlies the first surface of the second semiconductor die and contacts the edge surfaces of first portions of the second wire bonds, wherein second portions of the second wire bonds are defined by the end surfaces of the second wire bonds and portions of the edge surfaces of the second wire bonds extending from the end surfaces of the second wire bonds that are uncovered by and project above the surface of the compliant material layer overlying the front surface of the second semiconductor die.

2. The microelectronic structure of claim 1, wherein the second portions of the first wire bonds are moveable with respect to the bases thereof.

3. The microelectronic structure of claim 1, wherein the compliant material layer has a Young'"'"'s modulus of 2.5 GPa or less.

4. The microelectronic structure of claim 1, wherein the second portions of the first wire bonds extend along axes of the first wire bonds that are disposed at angles of at least 30 degrees with respect to the first surface of the compliant material layer.

5. The microelectronic structure of claim 1, wherein the end surfaces of the first wire bonds are positioned above the first surface of the compliant material layer by a distance of at least 50 microns.

6. The microelectronic structure of claim 1, wherein the first semiconductor die has a second surface opposite the first surface and a plurality of edge surfaces extending between the first and second surfaces, and wherein the compliant material layer further includes edge surfaces extending from the first surface of the compliant material layer thereof to the first surface of the first semiconductor die, the edge surfaces of the compliant material layer being substantially coplanar with the edge surfaces of the first semiconductor die.

7. The microelectronic structure of claim 1, wherein a first one of the first wire bonds has a shape such that the first one of the first wire bonds defines an axis between a free end of the first one of the first wire bonds and the base of the first one of the first wire bonds and such that the first one of the first wire bonds defines a plane, a bent portion of the first one of the first wire bonds extending away from the axis within the plane.

8. The microelectronic structure of claim 7, wherein the shape of the first one of the first wire bonds is further such that a substantially straight portion of the first one of the first wire bonds extends between the free end of the first one of the first wire bonds and the bent portion along the axis.

9. The microelectronic structure of claim 1, wherein the second region surrounds the first region of the first surface of the first semiconductor die.

10. A microelectronic structure, comprising:

a first semiconductor die having a first surface, the first surface having a first region and a second region, a plurality of first electrically conductive elements at the first surface of the first semiconductor die;

a second semiconductor die mounted on the first semiconductor die within the first region, the second semiconductor die has a front surface and a plurality of second electrically conductive elements at the front surface, wherein the front surface of the second semiconductor die faces away from the first surface of the first semiconductor die;

a plurality of first wire bonds having bases joined to respective ones of the first conductive elements, the first wire bonds further having end surfaces remote from the bases, the first wire bonds defining edge surfaces extending between the bases and the end surfaces thereof; and

a compliant material layer overlying the first surface of the first semiconductor die and overlying the second semiconductor die, the compliant material layer contacting edge surfaces of first portions of the first wire bonds and fully encapsulating each first portion such that the first portions of the first wire bonds are separated from one another by the compliant material layer, the compliant material layer further having a surface facing away from the first surface of the first semiconductor die, wherein second portions of the first wire bonds including the end surfaces are disposed above the surface of the compliant material layer, the second portions configured to connect with contacts of a substrate external to the microelectronic structure,

wherein the first portions of the first wire bonds are movable within the compliant material layer by deformation of the compliant material layer, such that, in a state of the microelectronic structure assembled with the substrate and the second portions of the first wire bonds connected with contacts of the substrate, such movement of the first wire bonds compensates for displacement of the contacts relative to the first conductive elements, such as caused by differential thermal expansion between the first semiconductor die and the substrate,

the microelectronic structure further comprising a plurality of second wire bonds having bases joined to the second electrically conductive elements and having free ends remote from the bases of the second wire bonds, the free ends of the second wire bonds remote from the first surface of the second semiconductor die, and the free ends of the second wire bonds including end surfaces of the second wire bonds, the second wire bonds defining edge surfaces extending between the bases of the second wire bonds and the end surfaces of the second wire bonds,

wherein the compliant material layer overlies the first surface of the second semiconductor die and contacts the edge surfaces of first portions of the second wire bonds, wherein second portions of the second wire bonds are defined by the end surfaces of the second wire bonds and portions of the edge surfaces of the second wire bonds extending from the end surfaces of the second wire bonds that are uncovered by and project above the surface of the compliant material layer overlying the front surface of the second semiconductor die.

11. The microelectronic structure of claim 10, wherein the second portions of the wire bonds are moveable with respect to the bases thereof.

12. The microelectronic structure of claim 10, wherein the first semiconductor die has a second surface opposite the first surface and a plurality of edge surfaces extending between the first and second surfaces, and wherein the compliant material layer further includes edge surfaces extending from the first surface of the compliant material layer thereof to the first surface of the first semiconductor die, the edge surfaces of the compliant material layer being substantially coplanar with the edge surfaces of the first semiconductor die.