Varied STI liners for isolation structures in image sensing devices

• US 10,008,531 B2
• Filed: 04/13/2015
• Issued: 06/26/2018
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Cheng-Hsien, Tsai, Chia-Shiung, Hung, Feng-Chi, Lu, Jiech-Fun, Kao, Min-Feng, Chou, Shih Pei, Tu, Yeur-Luen
• Primary Examiner(s): Wilczewski, Mary
• Application Number:
  US14/685,300
• Publication Number:
  US 20150279879A1
• Time in Patent Office: 1,170 Days
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.

Claims

1. An integrated circuit device comprising:

a sensor element isolated by a first isolation structure and a circuit element isolated by a second isolation structure;

wherein the first isolation structure is disposed in a substrate, the first isolation structure having a first liner layer and a first trench fill material, the first liner layer having a first thickness that is less than or equal to about 20 Angstroms, and

wherein the second isolation structure is disposed in the substrate, the second isolation structure having a second liner layer and a second trench fill material, the second liner layer having a second thickness that is greater than or equal to about 100 Angstroms, and the second isolation structure having a depth that is greater than the first isolation structure; and

wherein a portion of the substrate adjacent to the first isolation structure includes a junction isolation implantation region, and wherein a portion of the substrate adjacent to the second isolation structure is free of the junction isolation implantation region.

2. The integrated circuit device of claim 1, wherein the first liner layer and the second liner layer are thermal oxide layers formed by independent thermal oxidation processes.

3. The integrated circuit device of claim 1, wherein the substrate includes a first surface and a second surface, the first surface opposite the second surface, and further wherein the circuit element is a transistor that includes:

a gate structure disposed over the first surface of the substrate; and

a first source/drain region and a second source/drain region disposed in the substrate between the first isolation structure and the gate structure, such that the gate structure interposes the first source/drain region and the second source/drain region.

4. The integrated circuit device of claim 3, wherein the sensor element includes:

a light sensing region disposed in the substrate that extends from the first surface to the second surface;

a color filter disposed over the second surface of the substrate, such that the color filter is disposed over the light sensing region; and

a lens disposed over the second surface of the substrate, such that the lens is disposed over the color filter.

5. The integrated circuit device of claim 4, wherein the first surface is a front surface and the second surface is back surface.

6. The integrated circuit device of claim 2, wherein the first trench fill material and the second trench fill material is silicon oxide.

7. An integrated circuit device comprising:

a sensor element disposed between first isolation structures in a substrate, each of the first isolation structures including a first liner disposed on a portion of a substrate including a junction isolation implantation region; and

a transistor disposed between second isolation structures in a substrate, each of the second isolation structures including a second liner disposed on a portion of the substrate free of the junction isolation implantation region, wherein the first isolation structures have a first depth less than a second depth of the second isolation structures, and further wherein a first thickness of the first liner is less than a second thickness of the second liner;

wherein the substrate includes a front surface and a back surface, the first isolation structures and the second isolation structures extending from the front surface into the substrate towards the back surface;

wherein the transistor is disposed at the front surface and the sensor element includes a light sensing region disposed in the substrate;

a doped layer disposed on the back surface of the substrate, wherein the light sensing region extends from the front surface of the substrate to the doped layer;

a color filter disposed over the back surface of the substrate, wherein the color filter is aligned with the light sensing region; and

a lens disposed over the back surface of the substrate, wherein the lens is aligned with the light sensing region.

8. The integrated circuit device of claim 7, wherein the first isolation structures and the second isolation structures each include a fill material disposed respectively on the first liner and the second liner.

9. The integrated circuit device of claim 7, wherein the first thickness is less than about 20 Angstroms, and the second thickness is greater than or equal to about 100 Angstroms.

10. The integrated circuit device of claim 7, wherein the junction isolation implantation region is disposed adjacent to sidewalls of the first isolation structures.

11. The integrated circuit device of claim 7, wherein the sensor element further includes a reset transistor and a transfer transistor disposed at the front surface of the substrate between the first isolation structures.

12. The integrated circuit device of claim 7, wherein the first depth is less than or equal to about 1500 Angstroms, and wherein the second depth is between about 2500 Angstroms and about 3000 Angstroms.

13. The integrated circuit device of claim 7, wherein the junction isolation implantation region includes a boron dopant.

14. The integrated circuit device of claim 7, further comprising an antireflective layer disposed over the doped layer.

15. The integrated circuit device of claim 7, wherein the sensor element further includes a pinned layer disposed at the front surface of the substrate adjacent to the light sensing region, wherein a dopant type of the pinned layer is opposite a dopant type of the light sensing region.

16. A device comprising:

a substrate having a first portion associated with an image sensor and a second portion associated with a circuit element,

wherein the first portion includes a first isolation structure including a first thermal oxide liner disposed on the substrate,

wherein the second portion includes a second isolation structure including a second thermal oxide liner disposed on the substrate,

wherein a portion of the substrate adjacent to the first isolation structure includes a plasma-doped junction isolation implantation region, and a portion of the substrate adjacent to the second isolation structure is free of the plasma-doped junction isolation implantation region,

wherein the first thermal oxide liner and the second thermal oxide liner are formed by independent thermal oxidation processes, such that the first thermal oxide liner has a first thickness that is less than a second thickness of the second thermal oxide liner, wherein the first thickness is less than about 20 Angstroms, and wherein the second thickness is greater than or equal to about 100 Angstroms,

wherein the first isolation structure and the second isolation structure each include a fill material disposed respectively on the first thermal oxide liner and the second thermal oxide liner, and

wherein a depth of the first isolation structure is less than a depth of the second isolation structure.

17. The device of claim 16, wherein the plasma-doped junction isolation implantation region of the substrate includes boron.

18. The device of claim 16, wherein the first isolation structure is a deep trench isolation structure.