Semiconductor device and method of fabricating the same

• US 10,008,575 B2
• Filed: 10/20/2016
• Issued: 06/26/2018
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Dong Chan, Tak, Yong Suk, Park, Gi Gwan, Park, Mi Seon, Yang, Moon Seung, Lee, Seung Hun, Tang, Poren
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US15/298,746
• Publication Number:
  US 20170222006A1
• Time in Patent Office: 614 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

Claims

1. A semiconductor device, comprising:

a first wire pattern on a substrate, the first wire pattern isolated from the substrate;

a gate electrode surrounding and intersecting the first wire pattern;

a semiconductor pattern on at least two sides of the first wire pattern, the semiconductor pattern including a first part, the first part overlaps the first wire pattern;

a gate insulating layer between the gate electrode and the first wire pattern, and the gate insulating layer surrounding the first wire pattern; and

a first spacer between the first wire pattern and the substrate, and the first spacer between the gate insulating layer and the semiconductor pattern,

wherein the first part of the semiconductor pattern is between the substrate and the first wire pattern.

2. The semiconductor device of claim 1, wherein the first spacer includes a side, the side is between the first spacer and the gate insulating layer, and the side is curved.

3. The semiconductor device of claim 2, wherein the side is convex with respect to the gate electrode.

4. The semiconductor device of claim 1, wherein the first spacer includes a side that faces the semiconductor pattern, and the side of the first spacer is curved.

5. The semiconductor device of claim 4, wherein the side of the first spacer is convex with respect to the gate electrode.

6. The semiconductor device of claim 1, wherein,

the first spacer includes a first thickness and a second thickness, a first location of the first spacer having the first thickness, and a second location of the first spacer having the second thickness, the first thickness is different from the second thickness;

and

the first location is a first distance from an end of the first wire pattern, and the second location is a second distance from the end of the first wire pattern, the second distance is greater than the first distance.

7. The semiconductor device of claim 1, further comprising:

a plurality of lower spacer patterns, the plurality of lower spacer patterns including a first lower spacer pattern and a second lower spacer pattern, the first and second lower spacer patterns between the substrate and the semiconductor pattern, the first lower spacer pattern and the second lower space pattern spaced apart from each other.

8. The semiconductor device of claim 1, further comprising:

a first sacrificial pattern between the substrate and the semiconductor pattern, the semiconductor pattern contacts the first sacrificial pattern.

9. The semiconductor device of claim 1, further comprising:

a second wire pattern on the first wire pattern, the second wire pattern isolated from the first wire pattern,

wherein,

the gate electrode surrounds the second wire pattern,

the semiconductor pattern is on at least two sides of the second wire pattern,

the gate insulating layer is between the gate electrode and the second wire pattern, and the gate insulating layer surrounds the second wire pattern, and

the semiconductor pattern includes a second part, the second part overlaps the second wire pattern.

10. The semiconductor device of claim 9, further comprising:

a second spacer between the second wire pattern and the first wire pattern, and the second spacer between the gate insulating layer and the semiconductor pattern.

11. The semiconductor device of claim 1, wherein the semiconductor pattern is a source/drain region.

12. A semiconductor device, comprising:

a first wire pattern on a substrate, the first wire pattern isolated from the substrate;

a gate electrode surrounding and intersecting the first wire pattern;

a semiconductor pattern on at least two adjacent sides of the first wire pattern;

a gate insulating layer between the gate electrode and the first wire pattern, and the gate insulating layer surrounding the first wire pattern; and

a first spacer between the first wire pattern and the substrate, the first spacer between the gate insulating layer and the semiconductor pattern, and the first spacer including first and second sidewalls, the first and second sidewalls extend from the first wire pattern toward the substrate,

wherein at least one of the first and second sidewalls is convex toward the gate electrode.

13. The semiconductor device of claim 12, wherein a part of the semiconductor pattern overlaps the first wire pattern.

14. The semiconductor device of claim 12, wherein,

the first spacer includes a first thickness and a second thickness, a first location of the first spacer having the first thickness, and a second location of the first spacer having the second thickness, the first thickness is different from the second thickness;

and

the first location is a first distance from an end of the first wire pattern, and the second location is a second distance from the end of the first wire pattern, the second distance is greater than the first distance.

15. A semiconductor device, comprising:

a wire pattern on a substrate, the wire pattern isolated from the substrate and wherein the wire pattern extends in a first direction, comprises first and second sides that are adjacent to each other, the first side of the wire pattern is perpendicular to an upper surface of the substrate and the second side of the wire pattern extends in the first direction;

a gate electrode surrounding and intersecting the wire pattern;

a semiconductor pattern on the first and second sides of the wire pattern;

a gate insulating layer between the gate electrode and the wire pattern; and

a spacer on the second side of the wire pattern, the spacer between the semiconductor pattern and the gate insulating layer.

16. The semiconductor device of claim 15, wherein the spacer is convex with respect to the gate insulating layer.

17. The semiconductor device of claim 15, wherein the spacer includes a first thickness and a second thickness, the first thickness is different from the second thickness.

18. The semiconductor device of claim 17, wherein a first location of the spacer has the first thickness, the first location corresponds to a point of contact between the first side of the spacer and the wire pattern, the first thickness is less than the second thickness.

19. The semiconductor device of claim 18, wherein a second location of the spacer has the second thickness, the second location corresponds to a point of contact between the second side of the spacer and the gate insulating layer.

20. The semiconductor device of claim 15, wherein the semiconductor pattern is a source/drain region.