MOSFET with integrated schottky diode

• US 10,008,579 B2
• Filed: 06/17/2016
• Issued: 06/26/2018
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Calafut, Daniel, Lee, Yeeheng
• Primary Examiner(s): Pizzaro, Marcos D
• Assistant Examiner(s): Yi, Shannon
• Application Number:
  US15/185,860
• Publication Number:
  US 20160300924A1
• Time in Patent Office: 739 Days
• Field of Search: 257334
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66257 Schottky transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 : the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.

Claims

1. A method for forming Schottky structure comprising:

a) forming two trenches in a semiconductor material separated by a mesa;

b) lining sidewalls and a bottom surface of the trenches with a dielectric material;

c) disposing a conductive material in the trenches, wherein the disposed conductive material lines the dielectric material on the sidewalls and the bottom surface;

d) removing the conductive material on the bottom surface of the trenches, wherein a first portion of conductive material remains on a first sidewall of each trench, and wherein a second portion of conductive material remains on a second sidewall of each trench, and wherein the first and second portions of conductive material are electrically isolated from each other and are maintained at different electric potentials;

e) filling a space between the first and second portions of the conductive material with a trench filling insulator material; and

f) forming a Schottky contact between the outermost sidewalls of the two trenches.

2. The method of claim 1, wherein the two trenches are formed in an active region of a MOSFET device.

3. The method of claim 1, wherein the two trenches are formed in a termination region of a MOSFET device.

4. The method of claim 1, wherein a width of the mesa between the two trenches is equal to a width of a mesa between device trenches formed in the semiconductor material.

5. The method of claim 1, wherein a width of the mesa between the two trenches is smaller than an active device mesa separating device trenches.

6. The method of claim 1, wherein the Schottky contact is formed in the mesa between the two trenches.

7. The method of claim 1, wherein the Schottky contact is formed in one of the trenches between the first conductive portion and the second conductive portion.

8. The method of claim 1, wherein Schottky contacts are formed in both trenches between the first conductive portions and the second conductive portions.

9. The method of claim 1, wherein a first Schottky contact is formed in the mesa between the two trenches and a second Schottky contact is formed in at least one of the trenches between the first conductive portion and the second conductive portion.

10. The method of claim 1, wherein the Schottky structure is integrated into a bipolar transistor, insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET), a diode, a resistor or a capacitor.

11. The method of claim 2, wherein the first portion of conductive material in the first trench is maintained at a gate potential, the second portion of conductive material in the first trench is maintained at a source potential, the first portion of conductive material in the second trench is maintained at the source potential, and the second portion of conductive material in the second trench is maintained at the gate potential.

12. The method of claim 3, wherein the first portion of conductive material in the first trench is maintained at a gate potential, the second portion of conductive material in the first trench is maintained at a source potential, the first portion of conductive material in the second trench is maintained at the source potential, and the second portion of conductive material in the second trench is maintained at drain potential.

13. The method of claim 5, wherein the width of the mesa between the two trenches is between one fourth and three fourths of the width of the active device mesa.

14. The method of claim 6, wherein the Schottky contact further contacts the conductive portions in each trench proximate to the mesa.

15. The method of claim 8, wherein at least one of the Schottky contacts is deactivated by selectively doping the semiconductor material below one of the trenches with dopants configured to prevent a Schottky diode from forming.