Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

• US 10,008,662 B2
• Filed: 03/12/2015
• Issued: 06/26/2018
• Est. Priority Date: 03/12/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: You, Wen-Chun, Tu, Kuo-Chi, Chang, Chih-Yang, Chen, Hsia-Wei, Yang, Chin-Chieh, Shih, Sheng-Hung, Chu, Wen-Ting, Liao, Yu-Wen
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/645,683
• Publication Number:
  US 20160268499A1
• Time in Patent Office: 1,202 Days
• Field of Search: 438198
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A method of forming a magnetoresistive random access memory (MRAM) device including a perpendicular MTJ (magnetic tunnel junction) is provided. The method includes forming a magnetic tunneling junction (MTJ) over a bottom electrode layer. A top electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the top electrode layer. A first etch is performed through the top electrode layer, through regions of the MTJ unmasked by the hard mask, to form a top electrode and an etched MTJ. Sidewall spacers are formed extending from an upper surface of the hard mask or the top electrode, along sidewalls of the top electrode and the etched MTJ, to a point below or about even with an upper surface of the bottom electrode. A resulting MRAM device structure is also provided.

Claims

1. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a bottom electrode layer over a protective layer, the bottom electrode layer having a central portion that extends through the protective layer, and a peripheral portion having a lower surface in direct contact with an upper surface of the protection layer;

forming a magnetic tunneling junction (MTJ) over the bottom electrode layer;

forming a top electrode layer over an upper surface of the MTJ;

forming a dielectric hard mask over an upper surface of the top electrode layer;

performing a first etch which thins the dielectric hard mask and extends through the top electrode layer and through regions of the MTJ unmasked by the dielectric hard mask, and through an upper surface but not a lower surface of the bottom electrode layer to define a ledge, to form a top electrode and an etched MTJ with a thinned portion of the dielectric hard mask remaining in place over the top electrode; and

forming sidewall spacers extending from an upper surface of the thinned portion of the dielectric hard mask, along sidewalls of the top electrode and the etched MTJ, to an upper surface of the ledge of the bottom electrode layer;

wherein the MTJ includes;

a first ferromagnetic layer;

an insulating barrier layer disposed over the first ferromagnetic layer; and

a second ferromagnetic layer disposed over the insulating barrier layer, wherein magnetic polarities of the first ferromagnetic layer and the second ferromagnetic layer are perpendicular to an interface between the insulating barrier layer and the first ferromagnetic layer or the second ferromagnetic layer.

2. The method according to claim 1, wherein the first ferromagnetic layer is configured to switch between at least two magnetic polarities and the second ferromagnetic layer has a fixed magnetic polarity.

3. The method according to claim 1, wherein forming the sidewall spacers includes:

forming a sidewall spacer layer over the thinned portion of the dielectric hard mask, and lining the upper surface and sidewalls of the thinned portion of the dielectric hard mask and sidewalls of the etched MTJ; and

performing a second etch into the sidewall spacer layer to form the sidewall spacers.

4. The method according to claim 3, wherein the second etch further etches lateral stretches of the bottom electrode layer, to form a bottom electrode.

5. The method according to claim 4, further including:

forming a first capping layer that extends along the sidewall spacers, sidewalls of the bottom electrode and the sidewalls and the upper surface of the thinned portion of the dielectric hard mask;

forming a second capping layer that extends along sidewalls and upper surfaces of the first capping layer; and

depositing an interlayer dielectric (ILD) layer over upper surfaces and sidewalls of the second capping layer.

6. The method according to claim 5, further including:

photo patterning and etching the ILD layer to form a via opening and a trench; and

filling the via opening and the trench respectively with a metal layer to form a TEVA (top electrode via) and a metal trench.

7. The method according to claim 6, wherein the TEVA extends through the first capping layer, the second capping layer- and the thinned portion of the dielectric hard mask to abut the top electrode.

8. The method according to claim 4, further including:

performing a CMP (chemical mechanical polishing) process to planarize an upper surface of the top electrode and to form a planar top surface; and

depositing a top metal over the planar top surface and abutting the top electrode.

9. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a bottom electrode layer over a dielectric protective layer, the bottom electrode layer having a central portion that extends through the dielectric protective layer, and having a peripheral portion having a lower surface in direct contact with an upper surface of the dielectric protective layer;

forming a magnetic tunneling junction (MTJ) over the bottom electrode layer;

forming a top electrode layer over an upper surface of the MTJ;

forming an un-doped silicate glass (USG) hard mask over an upper surface of the top electrode layer;

performing a first etch which erodes the USG hard mask and which extends through the top electrode layer and through regions of the MTJ unmasked by the USG hard mask, and through an upper surface but not a lower surface of the bottom electrode layer to define a ledge, to form a top electrode and an etched MTJ with an eroded portion of the USG hard mask remaining in place over an upper surface of the top electrode;

forming sidewall spacers extending from an upper surface of the eroded portion of the USG hard mask, along sidewalls of the top electrode and the MTJ, to the ledge of the bottom electrode layer; and

wherein the sidewalls spacers have substantially uniform width from an upper surface of the eroded portion of the USG hard mask, to the ledge of the bottom electrode layer;

wherein forming the MTJ includes;

forming a first ferromagnetic layer over the bottom electrode;

forming an insulating barrier layer over the first ferromagnetic layer; and

forming a second ferromagnetic layer over the insulating barrier layer, wherein magnetic polarities of the first ferromagnetic layer and the second ferromagnetic layer are perpendicular to an interface between the insulating barrier layer and the first ferromagnetic layer or the second ferromagnetic layer.

10. The method according to claim 9, wherein the first ferromagnetic layer is configured to switch between at least two magnetic polarities and the second ferromagnetic layer has a fixed magnetic polarity.

11. The method according to claim 9, wherein forming the sidewall spacers includes:

forming a sidewall spacer layer over the USG hard mask, and lining the upper surface and sidewalls of the USG hard mask and sidewalls of the top electrode and the MTJ; and

performing a second etch into the sidewall spacer layer to form the sidewall spacers.

12. The method according to claim 11, wherein the second etch removes lateral stretches of the bottom electrode layer to form a bottom electrode.

13. The method according to claim 12, further including:

forming a first capping layer that extends along the sidewalls and upper surfaces of the sidewall spacers, along sidewalls of the bottom electrode, and along the sidewalls and the upper surface of the hard mask;

forming a second capping layer that extends along sidewalls and upper surfaces of the first capping layer; and

depositing an interlayer dielectric (ILD) layer over sidewalls and upper surfaces of the second capping layer.

14. The method according to claim 13, further including:

photo patterning and etching the ILD layer to form a via opening and a trench; and

filling the via opening and the trench respectively with a metal layer to form a top electrode via and a metal trench.

15. The method according to claim 14, wherein the top electrode via extends through the first capping layer, the second capping layer and the hard mask to abut the top electrode.

16. The method according to claim 12, further including:

performing a CMP (chemical mechanical polishing) process to planarize an upper surface of the top electrode and to form a planar top surface; and

depositing a top metal over the planar top surface and abutting the top electrode.

17. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a bottom electrode layer over a dielectric protective layer, the bottom electrode layer having a central portion that extends through the dielectric protective layer and a peripheral portion having a lower surface in direct contact with an upper surface of the dielectric protection layer;

forming a magnetic tunneling junction (MTJ) over the bottom electrode layer;

wherein forming the MTJ includes;

forming a first ferromagnetic layer over the bottom electrode layer;

forming an insulating barrier layer over the first ferromagnetic layer; and

forming a second ferromagnetic layer over the insulating barrier layer, wherein magnetic polarities of the first ferromagnetic layer and the second ferromagnetic layer are perpendicular to an interface between the insulating barrier layer and the first ferromagnetic layer or the second ferromagnetic layer;

forming a top electrode layer over an upper surface of the MTJ;

forming a dielectric hard mask over an upper surface of the top electrode layer;

performing a first etch through the top electrode layer and through regions of the MTJ unmasked by the dielectric hard mask, and through an upper surface of the bottom electrode layer to a depth within the bottom electrode layer to define a ledge, to form a top electrode and an etched MTJ; and

forming sidewall spacers in direct contact with sidewalls of the dielectric hard mask, the top electrode and the etched MTJ;

the sidewall spacers extending from an upper surface of the dielectric hard mask, along sidewalls of the top electrode and the etched MTJ, to the ledge of the bottom electrode layer.

18. The method according to claim 17, wherein the sidewall spacers comprise silicon nitride, silicon carbide, or a combination of silicon nitride and silicon carbide.