Three state latch

• US 10,009,027 B2
• Filed: 03/31/2017
• Issued: 06/26/2018
• Est. Priority Date: 06/04/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Gotterba, Andreas J., Wang, Jesse S.
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US15/476,847
• Publication Number:
  US 20170207783A1
• Time in Patent Office: 452 Days
• Field of Search: None
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/09425 Multistate logic H03K19/096 takes precedence
• CPC Class Codes: H03K 3/038 Multistable circuits

Abstract

Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Claims

1. An electronic circuit comprising:

n pairs of cascaded logical gates, wherein each of said pairs of cascaded logical gates comprises;

a first logical gate comprising n−

1 first gate inputs and a first gate output;

a second logical gate comprising two second gate inputs and a second gate output,

wherein one of said second gate inputs is coupled to said first gate output;

wherein said second gate output is cross coupled to one of said first gate inputs of all other said pairs of cascaded logical gates; and

where n is greater than 2.

2. The electronic circuit of claim 1 wherein said first and said second logical gates are rendered as a single OR-AND-INVERT gate.

3. The electronic circuit of claim 1 wherein said first logical gate comprises an OR gate.

4. The electronic circuit of claim 1 wherein said second logical gate comprises a NAND gate.

5. The electronic circuit of claim 1 wherein said first and said second logical gates comprise an AND-OR-INVERT gate structure.

6. The electronic circuit of claim 1 wherein said first logical gate comprises an AND gate.

7. The electronic circuit of claim 1 wherein said first logical gate comprises an NOR gate.

8. An electronic circuit comprising:

a single latch circuit comprising;

a first OR-AND-Invert (OAI) gate having an output coupled to an OR input of a second OAI gate and to an OR input of a third OAI gate;

said second OR-AND-Invert (OAI) gate having an output coupled to an OR input of said first OAI gate and to an OR input of said third OAI gate; and

said third OR-AND-Invert (OAI) gate having an output coupled to an OR input of said first OAI gate and to an OR input of said second OAI gate.

9. The electronic circuit of claim 8 wherein the output of said first, second and third OAI gates indicates a state of said single latch circuit.

10. The electronic circuit of claim 8 wherein each of said OAI gates output is configured to react to a change in said circuit inputs within a maximum of two gate delays.

11. The electronic circuit of claim 8 configured so that a zero on a NAND input of one of said OAI gates generates a one on the output of said one of said OAI gates.

12. The electronic circuit of claim 8 configured so that one on less than all NAND input of said first, second and third OAI gates forces a one on the output of the corresponding OAI gate.

13. The electronic circuit of claim 8 configured so that when all said NAND inputs of said single latch circuit are set to one, a previous state of the latch is retained.

14. An electronic circuit comprising:

a single latch circuit comprising;

n OR-AND-Invert (OAI) gates,

wherein an output of each said OAI gate is coupled to an input of n−

1 other said OAI gates; and

where n is greater than 2.

15. The electronic circuit of claim 14 wherein each of said OAI gates is configured to change its output responsive to a change at an input within a maximum of two gate delays.

16. The electronic circuit of claim 14 wherein said single latch circuit is configured to operate without a clock signal.

17. The electronic circuit of claim 14 wherein said single latch circuit has no transitory states.

18. The electronic circuit of claim 14 wherein said single latch circuit comprises 2_n−

1 stable states.

19. The electronic circuit of claim 14 wherein a zero on an input forces a corresponding output to one.

20. The electronic circuit of claim 14 wherein said single latch circuit comprises a maximum of 6n transistors.

21. An electronic circuit comprising:

n pairs of cascaded gates, wherein each of said pairs of cascaded gates comprises;

a first gate comprising n−

1 first gate inputs and a first gate output;

a second gate comprising two second gate inputs and a second gate output,

wherein one of said second gate inputs is coupled to said first gate output;

wherein said second gate output is coupled to one of said first gate inputs of n−

1 other said pairs of cascaded gates; and

where n is greater than 2.

22. The electronic circuit of claim 21 wherein said first and said second logical gates are rendered by not more than 6 transistors in total.