Cache management in a stream computing environment that uses a set of many-core hardware processors

• US 10,013,355 B1
• Filed: 10/04/2017
• Issued: 07/03/2018
• Est. Priority Date: 03/04/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cook, Alexander, Kleinheksel, Cory J., Koster, David M., Nikolai, Jason A.
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US15/724,360
• Time in Patent Office: 272 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.

Claims

1. A computer-implemented method for cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors, the method comprising:

detecting, for cache management in a stream computing environment, that a first cache and a second cache of a first core of a set of many-core hardware processors are local caches to the first core of the set of many-core hardware processors;

ascertaining using a system hardware diagnostic, for cache management in the stream computing environment, that a second cache size of the second cache of the first core of the set of many-core hardware processors exceeds a first cache size of the first cache of the first core of the set of many-core hardware processors, the second cache size and the first cache size indicating an amount of data storage available to the first cache and the second cache;

receiving a stream of tuples to be processed by a plurality of processing elements which operate on the set of many-core hardware processors;

computing, for cache management in the stream computing environment, a first cache utilization factor for the first cache of the first core of the set of many-core hardware processors;

computing, for cache management in the stream computing environment, a second cache utilization factor for the second cache of the first core of the set of many-core hardware processors;

determining, based on a cache factor associated with the set of many-core hardware processors, a tuple-processing hardware-route on the set of many-core hardware processors;

resolving, by comparing the first cache utilization factor for the first cache of the first core of the set of many-core hardware processors with the second cache utilization factor for the second cache of the first core of the set of many-core hardware processors, the tuple-processing hardware-route to prioritize utilization of the first cache of the first core of the set of many-core hardware processors with respect to the second cache of the first core of the set of many-core hardware processors;

ascertaining, for cache management in the stream computing environment, that a second cache access burden of the second cache of the first core of the set of many-core hardware processors exceeds a first cache access burden of the first cache of the first core of the set of many-core hardware processors;

routing, based on the tuple-processing hardware-route on the set of many-core hardware processors, the stream of tuples;

prioritizing, pertaining to processing the stream of tuples utilizing the set of many-core hardware processors, the first cache of the first core of the set of many-core hardware processors with respect to the second cache of the first core of the set of many-core hardware processors; and

processing, utilizing the set of many-core hardware processors, the stream of tuples by the plurality of processing elements which operate on the set of many-core hardware processors.