Configurable memory circuit system and method

• US 10,013,371 B2
• Filed: 11/22/2016
• Issued: 07/03/2018
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US15/358,335
• Publication Number:
  US 20170075831A1
• Time in Patent Office: 588 Days
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Claims

1. A sub-system, comprising:

an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to;

interface the plurality of physical memory circuits and the system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits;

receive a command from the system directed to the virtual memory circuit to perform the particular operation;

determine that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and

in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, perform a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits.

2. The sub-system of claim 1, wherein interfacing the plurality of physical memory circuits and the system to emulate the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the system, wherein the virtual memory circuit appears to the system as having the command operation period for performing the particular operation.

3. The sub-system of claim 1, wherein the virtual memory circuit has a larger memory capacity than a memory capacity of any one of the physical memory circuits.

4. The sub-system of claim 1, wherein the command comprises an activate command.

5. The sub-system of claim 1, wherein the command comprises a page open command.

6. The sub-system of claim 1, wherein performing the power-management on the second, different memory circuit of the plurality of physical memory circuits further comprises placing the second physical memory circuit in a power down mode.

7. The sub-system of claim 1, wherein performing the power-management on the second, different memory circuit of the plurality of physical memory circuits further comprises placing the second physical memory circuit in a pre-charge power down mode.

8. The sub-system of claim 1, wherein the command operation period is longer than a power down entry latency or a power down exit latency of a portion of the other physical memory circuits.

9. A method comprising:

interfacing, by an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the plurality of physical memory circuits and the system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits;

receiving a command from the system directed to the virtual memory circuit to perform the particular operation;

determining that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and

in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, performing a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits.

10. The method of claim 9, wherein interfacing the plurality of physical memory circuits and the system to emulate the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the system, wherein the virtual memory circuit appears to the system as having the command operation period for performing the particular operation.

11. The method of claim 9, wherein the virtual memory circuit has a larger memory capacity than a memory capacity of any one of the physical memory circuits.

12. The method of claim 9, wherein the command comprises an activate command.

13. The method of claim 9, wherein the command comprises a page open command.

14. The method of claim 9, wherein performing the power-management on the second, different memory circuit of the plurality of physical memory circuits further comprises placing the second physical memory circuit in a power down mode.

15. The method of claim 9, wherein performing the power-management on the second, different memory circuit of the plurality of physical memory circuits further comprises placing the second physical memory circuit in a pre-charge power down mode.

16. The method of claim 9, wherein the command operation period is longer than a power down entry latency or a power down exit latency of a portion of the other physical memory circuits.

17. A system, comprising:

a plurality of physical memory circuits; and

an interface circuit adapted for coupling with the plurality of physical memory circuits and a host system, the interface circuit configured to;

interface the plurality of physical memory circuits and the host system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits;

receive a command from the host system directed to the virtual memory circuit to perform the particular operation;

determine that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and

in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, perform a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits.

18. The system of claim 17, wherein interfacing the plurality of physical memory circuits and the host system to emulate the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the host system, wherein the virtual memory circuit appears to the host system as having the command operation period for performing the particular operation.

19. The system of claim 17, wherein the virtual memory circuit has a larger memory capacity than a memory capacity of any one of the physical memory circuits.

20. The system of claim 17, wherein performing the power-management on the second, different memory circuit of the plurality of physical memory circuits further comprises placing the second physical memory circuit in a power down mode.