Configurable memory circuit system and method
First Claim
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1. A sub-system, comprising:
- an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to;
interface the plurality of physical memory circuits and the system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits;
receive a command from the system directed to the virtual memory circuit to perform the particular operation;
determine that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and
in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, perform a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits.
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Abstract
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
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Citations
20 Claims
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1. A sub-system, comprising:
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an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to; interface the plurality of physical memory circuits and the system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits; receive a command from the system directed to the virtual memory circuit to perform the particular operation; determine that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, perform a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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interfacing, by an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the plurality of physical memory circuits and the system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits; receiving a command from the system directed to the virtual memory circuit to perform the particular operation; determining that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, performing a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system, comprising:
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a plurality of physical memory circuits; and an interface circuit adapted for coupling with the plurality of physical memory circuits and a host system, the interface circuit configured to; interface the plurality of physical memory circuits and the host system to emulate a virtual memory circuit having a command operation period for performing a particular operation on the virtual memory circuit that is longer than a latency associated with performing a power-management operation on a physical memory circuit of the plurality of physical memory circuits; receive a command from the host system directed to the virtual memory circuit to perform the particular operation; determine that the command is directed to a first physical memory circuit of the plurality of physical memory circuits; and in response to determining that the command is directed to the first physical memory circuit of the plurality of physical memory circuits, perform a power-management operation on a second, different physical memory circuit of the plurality of physical memory circuits. - View Dependent Claims (18, 19, 20)
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Specification