Multi-level message passing descriptor
First Claim
1. An apparatus comprising a processor, a logic and a memory, wherein the processor, logic and memory are operable to configure a data structure comprising:
- one or more second level descriptor; and
one or more first level linked list corresponding to the one or more second level descriptor;
wherein each second level descriptor comprises a data descriptor address for pointing to a corresponding first level linked list;
wherein each first level linked list comprises one or more first level descriptor;
wherein each first level descriptor comprises a buffer address for pointing to a data buffer; and
wherein at least one first level linked list and the one or more first level descriptor corresponding to the first level linked list is accessed by a first Direct Memory Access (DMA) channel and a second DMA channel for coordinated data transfer of the data buffer corresponding to the one or more first level descriptor.
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Accused Products
Abstract
In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.
364 Citations
20 Claims
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1. An apparatus comprising a processor, a logic and a memory, wherein the processor, logic and memory are operable to configure a data structure comprising:
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one or more second level descriptor; and one or more first level linked list corresponding to the one or more second level descriptor; wherein each second level descriptor comprises a data descriptor address for pointing to a corresponding first level linked list; wherein each first level linked list comprises one or more first level descriptor; wherein each first level descriptor comprises a buffer address for pointing to a data buffer; and wherein at least one first level linked list and the one or more first level descriptor corresponding to the first level linked list is accessed by a first Direct Memory Access (DMA) channel and a second DMA channel for coordinated data transfer of the data buffer corresponding to the one or more first level descriptor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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configuring a data structure in an apparatus comprising a processor, a logic and a memory, wherein the data structure comprises; one or more second level descriptor; and one or more first level linked list corresponding to the one or more second level descriptor; wherein each second level descriptor comprises a data descriptor address for pointing to a corresponding first level linked list; wherein each first level linked list comprises one or more first level descriptor; wherein each first level descriptor comprises a buffer address for pointing to a data buffer; and accessing at least one first level linked list and the one or more first level descriptor corresponding to the first level linked list by a first Direct Memory Access (DMA) channel and a second DMA channel for coordinated data transfer of the data buffer corresponding to the one or more first level descriptor. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An article of manufacture, comprising:
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a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising; configuring a data structure in the apparatus comprising a processor, a logic and a memory, wherein the data structure comprises; one or more second level descriptor; and one or more first level linked list corresponding to the one or more second level descriptor; wherein each second level descriptor comprises a data descriptor address for pointing to a corresponding first level linked list; wherein each first level linked list comprises one or more first level descriptor; wherein each first level descriptor comprises a buffer address for pointing to a data buffer; and accessing at least one first level linked list and the one or more first level descriptor corresponding to the first level linked list by a first Direct Memory Access (DMA) channel and a second DMA channel for coordinated data transfer of the data buffer corresponding to the one or more first level descriptor. - View Dependent Claims (18, 19, 20)
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Specification