Method for manufacturing semiconductor device using high speed epitaxial lift-off and template for III-V direct growth and semiconductor device manufactured using the same

• US 10,014,216 B2
• Filed: 09/15/2015
• Issued: 07/03/2018
• Est. Priority Date: 05/19/2015
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology
• Original Assignee: Korea Advanced Institute of Science and Technology
• Inventors: Kim, Sanghyeon, Geum, Daemyeong, Park, Min Su, Choi, Won Jun
• Primary Examiner(s): GONDARENKO, NATALIA A
• Application Number:
  US14/854,221
• Publication Number:
  US 20160343810A1
• Time in Patent Office: 1,022 Days
• Field of Search: 257183, 257 52, 257614, 257506, 257629, 257E21567, 257E29003, 257E29094, 257E27112, 257E29002, 257 76, 257615, 438455, 438478, 438483
• CPC Class Codes: H01L 21/185 Joining of semiconductor bodies for junction formation
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66219 with a heterojunction, e.g. resonant tunneling diodes [RTD]
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/184 the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a template having a first substrate and a patterned first III-V group compound layer disposed on the first substrate, wherein the providing of the template includes forming the patterned first III-V group compound layer by patterning the first III-V group compound layer on a first sacrificial layer;

forming an etch stop layer, apportioned according to a shape of the patterned first III-V group compound layer without additional patterning process, on the patterned first III-V group compound layer by epitaxial growth;

forming a second sacrificial layer on the etch stop layer by the epitaxial growth;

forming a second III-V group compound layer on the second sacrificial layer by the epitaxial growth;

bonding a second substrate made of silicon onto the second III-V group compound layer; and

separating the second III-V group compound layer and the second substrate from the template by removing the second sacrificial layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the bonding of a second substrate includes directly bonding the second III-V group compound layer and the second substrate to each other.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the bonding of the second substrate includes:

forming an adhesive layer on at least one of the second III-V group compound layer and the second substrate; and

bonding the second III-V group compound layer and the second substrate to each other by using the adhesive layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the adhesive layer includes metal or oxide.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the separating of the second III-V group compound layer and the second substrate from the template includes removing the second sacrificial layer by using a hydrophilic etching solution containing hydrogen fluoride (HF).

6. The method for manufacturing a semiconductor device according to claim 5, wherein the etching solution further contains at least one of isopropyl alcohol and acetone.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the providing of the template further includes:

forming an first etch stop layer on a support substrate having an III-V group compound;

forming the first sacrificial layer on the first etch stop layer;

forming the III-V group compound on the first sacrificial layer on the support substrate by epitaxial growth;

patterning the first sacrificial layer and the III-V group compound on the support substrate to form the patterned first III-V group compound layer; and

transferring the patterned first III-V group compound layer onto the first substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the forming of the patterned first III-V group compound layer includes etching the first sacrificial layer and the III-V group compound on the support substrate by using an etching solution containing phosphoric acid (H₃PO₄).

9. The method for manufacturing a semiconductor device according to claim 7, wherein the transferring onto the first substrate includes:

bonding the support substrate, the first sacrificial layer on the support substrate and the patterned first III-V group compound layer to the first substrate so that the patterned first III-V group compound layer contacts the first substrate; and

removing the first sacrificial layer on the support substrate after the bonding to separate the support substrate from the first substrate.

10. The method for manufacturing a semiconductor device according to claim 1, wherein

the first substrate is made of GaAs, and the etch stop layer is made of indium gallium phosphide (InGaP), or indium phosphide (InP), such that the etch stop layer is not dissolved during an etching process.

11. The method for manufacturing a semiconductor device according to claim 5, wherein the separating of the second III-V group compound layer and the second substrate from the template further includes removing the etch stop layer.

12. The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate is made of indium phosphide (InP), and the etch stop layer is made of indium gallium arsenide (InGaAs), such that the etch stop layer is not dissolved during an etching process.

13. A method for manufacturing a semiconductor device, comprising:

providing a template having a first substrate and a patterned first III-V group compound layer disposed on the first substrate;

forming an etch stop layer, apportioned according to a shape of the patterned first III-V group compound layer without additional patterning process, on the patterned first III-V group compound layer by epitaxial growth;

forming a sacrificial layer on the etch stop layer by the epitaxial growth;

forming a second III-V group compound layer on the sacrificial layer by the epitaxial growth;

bonding a second substrate made of silicon onto the second III-V group compound layer; and

separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer, wherein

the etch stop layer is not dissolved during an etching process using an etching solution in the removing of the sacrificial layer.