Methods of forming memory arrays
First Claim
Patent Images
1. A method of forming a memory array, comprising:
- forming a conductive wordline extending along a first direction, and along a rail of semiconductor material;
after forming the conductive wordline, patterning fins from the rail;
each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;
forming digit lines electrically coupled with the second pedestals; and
forming charge-storage devices electrically coupled with the first pedestals.
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Abstract
Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.
18 Citations
19 Claims
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1. A method of forming a memory array, comprising:
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forming a conductive wordline extending along a first direction, and along a rail of semiconductor material; after forming the conductive wordline, patterning fins from the rail;
each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;forming digit lines electrically coupled with the second pedestals; and forming charge-storage devices electrically coupled with the first pedestals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a memory array, comprising:
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forming a pair of conductive wordlines extending along a first direction, and spaced from one another by a rail of semiconductor material; forming at least one digit line material over the rail of semiconductor material; slicing the at least one digit line material into digit lines with a pattern, and after the forming of the pair of the conductive wordlines, utilizing the same pattern during etching into the rail to form fins;
each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;
the digit lines being electrically coupled with the second pedestals; andforming capacitors electrically coupled with the first pedestals. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming a memory array, comprising:
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forming a plurality of conductive wordline pairs extending along a first direction and along rails of semiconductor material;
each conductive wordline pair comprising a first conductive wordline and a second conductive wordline;
the first and second conductive wordlines of each of the conductive wordline pairs being spaced from one another by one of the rails of semiconductor material;forming an expanse extending across the rails of semiconductor material;
the expanse comprising at least one digit line material;slicing the expanse into a plurality of linear structures comprising the at least one digit line material;
the linear structures alternating between first linear structures and second linear structures;
the first linear structures being digit lines;
the slicing utilizing a pattern, and after the forming of the plurality of the conductive wordline pairs, the same pattern being used during etching into the rails to form fins;
each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;
the digit lines being electrically coupled with the second pedestals;dividing the at least one digit line material of the second linear structures into conductive interconnects electrically coupled with the first pedestals; and forming capacitors electrically coupled with the conductive interconnects. - View Dependent Claims (17, 18, 19)
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Specification