Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges

• US 10,014,365 B2
• Filed: 07/29/2014
• Issued: 07/03/2018
• Est. Priority Date: 04/13/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blanchard, Richard A.
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US14/445,942
• Publication Number:
  US 20170352724A1
• Time in Patent Office: 1,435 Days
• Field of Search: None
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Claims

1. A method for fabricating a power device, comprising the steps of:

etching one or more trenches vertically into a semiconductor mass;

forming a thin dielectric layer on sidewalls of said trenches;

introducing permanent electrostatic charge into said thin dielectric layer;

anisotropically etching through the bottoms of said trenches into said semiconductor mass; and

at least partially filling said trenches with a semiconductor material which is electrically connected to said semiconductor mass at the bottoms of said trenches.

2. The method of claim 1, further comprising a source, a body, and a gate which is capacitively coupled to control inversion of a nearby portion of said body.

3. The method of claim 1, wherein said trenches have permanent electrostatic charge in proximity to sidewalls thereof.

4. The method of claim 1, wherein the material trench filling said trenches material is silicon.

5. The method of claim 1, wherein said semiconductor mass is silicon, and said thin dielectric layer is silicon dioxide.

6. The method of claim 1, wherein the material filling said trenches is a substantially crystalline semiconductor material.

7. The method of claim 1, wherein the material filling said trenches is substantially the same semiconductor material as parts of said semiconductor mass outside said trenches.

8. The method of claim 1, wherein said semiconductor mass is silicon.

9. A method for fabricating a power device, comprising the steps of:

etching one or more trenches vertically into a semiconductor mass;

forming a thin dielectric layer on sidewalls of said trenches;

introducing permanent electrostatic charge into said thin dielectric layer;

anisotropically etching through the bottoms of said trenches into said semiconductor mass; and

at least partially filling said trenches with a semiconductor material which is electrically connected to said semiconductor mass at the bottoms of said trenches.

10. The method of claim 9, wherein said filling step uses the same semiconductor material as parts of said semiconductor mass outside said trenches.

11. The method of claim 9, wherein said semiconductor mass is silicon.

12. The method of claim 9, further comprising a source, a body, and a gate which is capacitively coupled to control inversion of a nearby portion of said body.

13. The method of claim 9, wherein said trenches have permanent electrostatic charge in proximity to sidewalls thereof.

14. The method of claim 9, wherein said filling step uses selective epitaxial growth.

15. The method of claim 9, wherein said filling step fills said trenches with silicon.

16. A method for fabricating a power device, comprising the steps of:

etching a plurality of trenches vertically into a semiconductor mass, both in the location of an array of active devices and also in a periphery around said array of active devices;

said trenches in said periphery having graded widths which become progressively smaller outside said array of active devices; and

angle-implanting ions into said trenches to thereby create permanent electrostatic charge at trench sidewalls which are thereby implanted;

said angle-implanting step being performed at an angle where bottoms of the trenches with the smallest of said widths are not exposed;

wherein said trenches in said periphery have graduated electrical properties outside said array of active devices.

17. The method of claim 16, wherein said angle-implanting step implants cesium ions.

18. The method of claim 16, wherein said semiconductor mass is silicon.

19. The method of claim 16, wherein said active devices are trench-gate transistors.